Brisbane Silicon publishes DPTx 1.4 IP Core
April 19, 2024 -- Today we are very excited to announce that Brisbane Silicon will add a DPTx 1.4 IP core to its IP library suite. A summary of this IP:
- DisplayPort 1.4 compatible.
- Ultra-small footprint (1k LUT minimum, 3.5k LUT maximum).
- Hardware proven on AMD/Xilinx 28nm FPGA fabric.
- Ships with an example project which demonstrates the following:
- Link initialization at 5.4 Gbps.
- Initialization of the DPTx core.
- Output a test video pattern with 4k60 framing.
- Commercial or Academic licenses available.
The hardware target for the example project is the Numato Mimas A7 FPGA Development board. See here for further information on this board.
Ad |
ASIL-B Ready ISO 26262 Certified VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter ![]() DisplayPort Transmitter Link Controller ![]() DisplayPort 1.4a IP Core ![]() |
For more information on the DPTx IP core, see the product summary available here.
|
Related News
- Renode 1.4 released: 64-bit RISC-V HiFive Unleashed support, multiple Silicon Labs targets, and more
- VESA Publishes DisplayPort Standard Version 1.4
- Silicon Image Introduces New IP Core Product Family Supporting HDMI(R) 1.4 Features
- Silicon Image Introduces First Products Incorporating HDMI 1.4 Features for DTV and Home Theatre Applications
- eDP/DP 1.4 Tx PHY & Controller IP Cores Now Available to Meet Rising Demand for High-Performance Display Solutions with Next-Gen Visual Connectivity
Breaking News
- Arteris Wins Two Gold and One Silver Stevie® Awards in the 2025 American Business Awards®
- Faraday Adds QuickLogic eFPGA to FlashKit‑22RRAM SoC for IoT Edge
- Xylon Introduces Xylon ISP Studio
- Crypto Quantique announces QRoot Lite - a lightweight and configurable root-of-trust IP for resource-constrained IoT devices
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
Most Popular
- Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
- Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
- M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |