M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process

Hsinchu, Taiwan - April 25, 2024 -- M31 Technology Corporation (M31), a leading global provider of silicon intellectual property (IP), announced that the M31 MIPI C/D-PHY Combo IP has obtained silicon validation on the advanced TSMC 5nm process and the company has already started 3nm IP development. These validated C-PHY and D-PHY IPs are capable of supporting high-speed transmission modes up to 6.5G per channel and extremely low power operation, making the IPs suitable for various application scenarios such as high-resolution imaging, display SoCs, advanced driver assistance systems (ADAS) and in-vehicle infotainment systems. This IP design allows users to configure it according to their needs as either D-PHY or C-PHY mode, further reducing the need for die area and the demand for I/O pins by sharing part of the circuit design. Additionally, it supports Alternate Low Data (ALP) mode, which significantly improves transfer efficiency while maintaining extremely low power consumption, making it particularly suitable for battery-powered mobile devices.

M31 has been honored with the TSMC Open Innovation Platform^® (OIP) Partner of the Year Award for Special Process IP for six consecutive years. At the TSMC 2024 North America Technology Symposium, M31 showcased two major product lines, including Foundation IP such as Standard Cell, Memory Compiler, GPIO, Specialty I/O, as well as the most popular high-speed interface IPs in the current application market, such as PCIe 5.0 PHY, ONFi 5.1 I/O, LPDDR4/4X PHY, and LPDDR5/5X PHY. M31 also introduced the 5nm MIPI C/D PHY Combo IP that complies with the latest D-PHY v2.5 and C-PHY v2.0 specifications. This IP offers a high-performance, low-power solution with speeds of up to 6.5Gb/s per channel and 6.5Gs/s per trio, for a total speed of up to 44.5Gb/s, meeting the current demands for high-speed data transmission, especially for diverse applications such as mobile communications, automotive, artificial intelligence (AI) and Internet of Things (IoT). In addition, MIPI technology also supports low-power state modes by consuming less than 1.1pJ/bit of power at maximum speed, and provides extensive built-in test capabilities, including pattern generators, logic analyzers, and loopback modes, facilitating testing and debugging for developers. Moreover, M31 supports key features of MIPI display and camera specifications, and makes it suitable for applications in ADAS and in-car infotainment systems, which meets the industry's stringent requirements for high reliability and functional safety. The M31 provides a rich portfolio of MIPI-related IPs that can be quickly integrated into SoCs to meet the design requirements of a wide range of applications.

Jerome Hung, Vice President of R&D, stated, “M31's innovative development in high-speed interface technology and in-depth understanding of systems enable us to respond to customer needs in rapidly changing markets by providing solutions that comply with the latest standards. Looking ahead, M31 will closely follow TSMC's advanced process technology, continue to invest in R&D resources, develop products using advanced process technology, and expand IP solutions in emerging application areas such as AI, IoT, and 5G communication, to help customers accelerate product launches and enhance market competitiveness.”

Head of TSMC OIP Ecosystem-Dan Kochpatcharin (third from left) takes a group photo with M31 Vice President of R&D-Jerome Hung(third from right), M31 North America General Manager-Kuoshu Chiu(first from left), and M31 professional team at the TSMC 2024 North America Symposium in Santa Clara.

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