Faraday's Configurable Array Brings Flexibility and Accelerated Time-to-Market for ASIC
HSINCHU, TAIWAN – June 2, 2003- Faraday Technology Corporation, a leading IP and ASIC design service company, today introduced its Three-Mask Programmable Cell Array (3MPCA) family, a high-performance, high-density and easy-to-use re-configurable cell array for UMC 0.35 ìm, 0.25 ìm, 0.18 ìm, 0.15 ìm and 0.13 ìm CMOS processes.
As semiconductor processing migrates to deep sub-micron, the corresponding tooling costs and mask charges also increase significantly. The time to market pressure, frequent feature changes and product derivatives only exacerbate the cost issues further. With its standard cell compatible performance, power efficiency and industry-leading array density, Faraday's 3MPCA helps users drastically reduce mask NRE (Non-Recurring Engineering), and re-spin costs and accelerate time-to-market.
Unlike other one-mask programmable cell arrays which have all their metal layers predefined, Faraday's 3MPCA adopts two top metal layers and one top via mask to do the function programming and interconnects. Customers may create a chip level platform for specific application by adding 3MPCA, originally verified circuit, and selected silicon IP in a chip design. This approach creates a "just-fit" routing plate and array structure hence achieving much higher array density and faster speed than those of one-mask programmable arrays. Compared with FPGA that uses SRAM cells to program the entire array, the 3MPCA boasts standard-cell-like performance while maintaining more than a magnitude better area density than that of FPGA.
"We see an ever increasing need for cost saving and demands for extending product life cycle," said H.P. Lin, President of Faraday Technology. "Our customers can enjoy accelerated development cycles and lower derivatives costs by adopting the winning combination of Faraday's 3MPCA technology, mass-production proven IP portfolios and state-of-the-art ASIC services," added Mr. Lin.
The 3MPCA can implement any type of combinational and sequential logics and it supports unlimited number of clock domains and gated clocks. "Easy-to-Use" is another important feature of Faraday 3MPCA; it uses existing ASIC design flow, so no additional CAD tool is required. For more information on Faraday's 3MPCA technology, please contact:
3MPCA Technology
The 3MPCA body is composed of a large number of basic blocks. Each block is capable of performing any combinational and sequential functions and comprises several Look-Up-Table (LUT) cells, driving cells, and storage elements. The 3MPCA boasts the best performance, lowest power consumption and class-leading area density on the market.
Features
- Core size range from 2,000 to 5 million ASIC gates
- Support unlimited clock domains and gated clocks
- Size and speed close to that of standard cell implementation
- Very low system power
- Built-in scan-chain
- No new investment regarding EDA tools and design flow is required
Benefits
- Radically drops overall NRE cost
- Pre-verified silicon ensures first-time working ASIC
- Offers complete IP portfolio – "design-to-silicon"
- Drastically reduces time-to-market by providing silicon-proven IP/cell library
- Significantly lowers re-spin cost and wafer processing time
- Greatly improves design predictability
Availability
The 3MPCA is available today for UMC 0.35 ìm, 0.25 ìm, 0.18 ìm, 0.15 ìm and 0.13 ìm CMOS processes for ASIC and IP customers.
About Faraday Technology Corporation
Faraday Technology Corporation provides leading ASIC/SoC design services and production-proven IPs to customers ranging from system houses and IDMs to IC design houses. The company's broad portfolio of key IPs includes leading products such as RISC CPUs, 16/20/24-bit DSPs, USB 2.0, gigabit Ethernet, and Serial-ATA. Faraday's ASIC design services and IPs are widely used in PC peripherals, communication, and digital consumer products. With more than 460 employees and 2002 revenue of 96.2 million USD, Faraday is the largest fabless ASIC design service company in all Asia-Pacific. Headquartered in Hsinchu Taiwan, Faraday offers service and support branch offices around the world, including the U.S., Japan, Europe, and China. For more information on Faraday, please visit http://www.faraday.com.tw
|
Faraday Technology Corp. Hot IP
Related News
- LSI Logic Brings New Dimension to Consumer Devices; ZEVIO processor architecture speeds time-to-market and enables low-cost, low-power 3D graphics and sound features for today's hottest consumer electronics products
- Faraday Offers Peripheral Composer, the Fastest Time-to-Market Structured ASIC for Peripheral Interface Chips
- Sandbridge Selects Barcelona's Analog Solutions to Speed Up Time-to-Market and Increase Flexibility
- Agere Systems Adopts LogicVision Technology to Improve Quality and Speed Time-to-Market for Agere's Gigabit Ethernet Chips
- AMCC's Comprehensive, Low-Cost PowerPC 440EP Evaluation Kit Accelerates Customers' Time-to-Market
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |