LogicVision Unveils Instant Characterization of SOC Cores At Design Automation Conference

Validator and hierarchical embedded test combination offers significant benefit to SoC designers and product engineers

San Jose, Calif. - May 30, 2003 - LogicVision, Inc., (NASDAQ:LGVN), a leading provider of embedded test for integrated circuits and systems, today announced new extensive SOC device and core characterization capabilities, using hierarchical embedded test and the LV ValidatorTM, that will be demonstrated at the upcoming Design Automation Conference (DAC). The ability to characterize individual embedded cores is an industry first. With traditional testing, it is not possible to apply tests to a single block in an SOC device while isolating all other blocks.

"LogicVision's hierarchical solution provides complete and self-contained tests for each user selected core, while the LV Validator and its Embedded Test Access (ETA) software enable full characterization under different test conditions in a matter of minutes", said Mukesh Mowji, vice president of sales and marketing.

Specific benefits available with this new capability are:

Determine maximum operating conditions over different voltage and frequency conditions.
Analyze process variations across the die through a hierarchical test approach that will determine speed of operation on a per block basis, linked directly to the physical layout of the chip.
Perform real-time power analysis of the device using the same hierarchical approach to determine power consumption of individual cores.
Optimize test throughput, determining the optimal test flow by evaluating tradeoffs between power and parallel testing of cores.
Perform root cause analysis of any marginal test condition, diagnosing memories to failing cells and logic to failing gates.

About LogicVision Inc.
LogicVision (NASDAQ: LGVN) provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com.

FORWARD LOOKING STATEMENTS:
Except for the historical information contained herein, the matters set forth in this press release, including statements as to the expected features and benefits of LogicVision's technology and products, such as characterization benefits to SOC designers and product engineers, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risk and uncertainties that could cause actual results to differ materially, including, but not limited to, the impact of competitive products and technological advances, and other risks detailed in LogicVision's Form 10-Q for the quarter ended March 31, 2003, and from time to time in LogicVision's SEC reports. These forward-looking statements speak only as of the date hereof. LogicVision disclaims any obligation to update these forward-looking statements.

LogicVision, Embedded Test, LogicVision Ready and LogicVision logos are trademarks or registered trademarks of LogicVision Inc. in the United States and other countries. All other trademarks and service marks are the property of their respective owners.

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