JEDEC Approaches Finalization of HBM4 Standard, Eyes Future Innovations
ARLINGTON, Va., USA – July 10, 2024 – JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced it is nearing completion of the next version of its highly anticipated High Bandwidth Memory (HBM) DRAM standard: HBM4. Designed as an evolutionary step beyond the currently published HBM3 standard, HBM4 aims to further enhance data processing rates while maintaining essential features such as higher bandwidth, lower power consumption, and increased capacity per die and/or stack. These advancements are vital for applications that require efficient handling of large datasets and complex calculations, including generative artificial intelligence (AI), high-performance computing, high-end graphics cards, and servers.
HBM4 is set to introduce a doubled channel count per stack compared to HBM3, with a larger physical footprint. To support device compatibility, the standard ensures that a single controller can work with both HBM3 and HBM4 if needed. Different configurations will require various interposers to accommodate the differing footprints. HBM4 will specify 24 Gb and 32 Gb layers, with options for supporting 4-high, 8-high, 12-high and 16-high TSV stacks. The committee has initial agreement on speeds bins up to 6.4 Gbps with discussion ongoing for higher frequencies.
JEDEC encourages companies to join and help shape the future of JEDEC standards. Membership grants access to pre-publication proposals and provides early insights into active projects like HBM4. Discover the benefits of membership and join today.
JEDEC standards are subject to change during and after the development process, including disapproval by the JEDEC Board of Directors.
About JEDEC
JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing over 350 member companies work together in more than 100 JEDEC committees and task groups to meet the needs of every segment of the industry, for manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for download from the JEDEC website. For more information, visit https://www.jedec.org.
|
Related News
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
- JEDEC Releases New Standard for LPDDR5/5X Serial Presence Detect (SPD) Contents
- JEDEC Updates JESD79-5C DDR5 SDRAM Standard: Elevating Performance and Security for Next-Gen Technologies
- JEDEC Publishes GDDR7 Graphics Memory Standard
- JEDEC Publishes New CAMM2 Memory Module Standard
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |