Consortium brings 'Spirit' to IP integration
Consortium brings 'Spirit' to IP integration
By Michael Santarini, EE Times
June 3, 2003 (9:19 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030603S0022
ANAHEIM, Calif. A new silicon intellectual property (IP) consortium, called Spirit (Structure for Packaging, Integrating, and Re-using IP within Tool flows), was launched Monday (June 2) at the Design Automation Conference (DAC) here. The consortium aims to ensure IP metadata can be easily transferred between IP vendors, EDA companies, semiconductor and systems companies.
Related News
- Mentor Graphics Platform Express is the First Platform-Based Design Solution to Support The SPIRIT Consortium's New Specification
- 'Spirit' consortium claims progress on IP tool
- Synopsys' coreAssembler Reduces Time and IP Integration Risk for Spirit-Compliant IP
- Spirit consortium releases IP integration standard
- NEDO Approves Rapidus' FY2024 Plan and Budget for "Research and Development of 2nm-generation semiconductor integration technology and short TAT manufacturing technology based on Japan-US collaboration"
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |