English
Xylon's Updated logiHSSL IP Core Seamlessly Connects Infineon AURIX Microcontrollers with AMD Adaptive SoCs and FPGAs
October 7, 2024 -- Xylon has announced significant architectural improvements to its popular logiHSSL Slave HSSL Controller IP core, widely used in various field applications over the past several years. The new design results in a more compact, resource-efficient IP core, enhancing its overall performance and usability.
The updated logiHSSL IP Core introduces a "reduced IP configuration," supporting one HSSL target device and one streaming data channel. Based on Xylon's experience, this configuration meets the needs of the vast majority of logiHSSL IP users. Compared to the maximum configuration, which supports up to four HSSL target and initiation devices, the reduced version saves approximately 50% of valuable programmable logic resources.
| Related |
Slave HSSL Controller  |
Specifically designed for AMD FPGAs and adaptive SoCs, the logiHSSL IP Core enables seamless data exchange between Infineon’s AURIX™ TC2xx, TC3xx, TC4xx microcontrollers and AMD programmable devices via the Infineon High-Speed Serial Link (HSSL). This enables system developers to combine the safety and security of AURIX microcontrollers with the versatile functionality of AMD devices. Through the HSSL, linked devices can access and control each other’s internal and connected resources.
To accelerate development in automotive and industrial applications, Xylon offers the logiHSSL-ZU FPGA HSSL Starter Kit. This comprehensive kit includes a hardware platform built from the AMD Zynq™ UltraScale+™ SoC-based ZCU104 Evaluation Kit and the Infineon AURIX Evaluation Board, along with necessary cabling and a fully functional reference hardware design.
Both the logiHSSL IP Core and the Starter Kit are now available through Xylon. For more information, please contact Xylon or visit our website: https://www.logicbricks.com/Products/logiHSSL.aspx.
|
||||||
Xylon Hot IP
Related News
- Xylon Announces New logicBRICKS Vision AI Framework for AMD Adaptive SoCs
- AMD Introduces World's Largest FPGA-Based Adaptive SoC for Emulation and Prototyping
- MIPI RFFE (RF Front-End Control Interface) v3.0 Master and Slave Controller IP Cores for ultimate control of your RF Front-end Cellular or Base station SoC's with Low Power Consumption and Reduced Latencies
- Synopsys Expands Portfolio of Automotive VDKs with Support for Infineon's AURIX TC4xx 32-bit Microcontroller Family
- Xylon's MPSoC Multi-Camera Vision Kit Updated
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |