DisplayPort Rx PHY and Controller IP Cores in multiple Leading Technology Nodes for Next-Generation Video SoCs

Oct 14^th, 2024 -- T2M-IP, the global leader in semiconductor IP cores and technology expertise, is proud to announce the immediate availability of its partner's VESA-compliant DisplayPort v1.4 Rx PHY and Controller IP Cores. These cores, designed for next-generation video SoCs, are silicon-proven across major foundries and optimized for low power consumption and exceptional efficiency, delivering a true UHD experience.

The DisplayPort 1.4 Rx PHY and Controller IP Core from T2M-IP integrates visually lossless compression technologies such as Display Stream Compression (DSC) and Forward Error Correction (FEC), enabling seamless 8K UHD display at 60Hz. Supporting data rates from 1.62Gbps (RBR) to 8.1Gbps (HBR3), this robust yet energy-efficient core is fully compliant with DisplayPort version 1.4 standards. Its programmable analog features, including inbuilt 100-ohm termination resistors with common-mode biasing and integrated variable-strength equalization, further enhance power efficiency.

The IP Core leverages packetized data transfer in popular process node technologies, enabling higher-resolution displays with fewer pins. DisplayPort 1.4 supports the transmission of Ultra High Definition (UHD) and High Dynamic Range (HDR) video streams via a single interface, making it ideal for high-end display applications requiring 8K resolution. Additionally, the core supports HDCP 1.4, HDCP 2.2, and DSC for bandwidth optimization. We understand developing robust video SoCs involves challenges in bandwidth, power efficiency, real-time processing, integration, standards support, and security.

The DisplayPort version 1.4-compliant receiver offers backward compatibility, customizable (4/2/1) link channels, and one AUX channel. It supports all recommended link and bit rates (1.62/2.7/5.4/8.1Gbps HBR3) and allows for main link operation using 1, 2, or 4 lanes. Features include SST mode, scrambler seed reset, enhanced/default framing modes, and programmable configuration registers via an AMBA interface.

The DisplayPort v1.4 Rx Controller and PHY IP, with its efficient lossless video compression, is widely adopted in computing, digital displays, monitors, TVs, and other consumer electronics, ensuring high-performance video data transfer for next-generation display technologies.

In addition to DisplayPort Rx IP Cores, T2M's extensive silicon Interface IP Core portfolio includes a wide range of solutions such as USB, HDMI, MIPI (CSI, DSI, UniPro, UFS, Soundwire, I3C), PCIe, DDR, 10/100/1000 Ethernet, V-by-One, programmable SerDes, Serial ATA, and more. These IP Cores are available in leading fabs and support advanced process geometries down to 7nm. Additionally, they can be ported to other foundries and cutting-edge process nodes upon request.

Availability:

These semiconductor interface IP Cores are available for immediate licensing, either as standalone solutions or pre-integrated with Controllers and PHYs, offering seamless integration into various SoC designs. For more information on customization, licensing options, and pricing, please submit a request to our team MailTo.

About T2M:

T2M-IP is a global leader in independent semiconductor technology, offering advanced semiconductor IP Cores, software solutions, Known Good Die (KGD), and disruptive technologies that drive accelerated development for Wearables, IoT, Communications, Storage, Servers, Networking, TV, Set-Top Box (STB), and Satellite SoCs. For more information, please visit: www.t-2-m.com

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