Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification
Hsinchu, Taiwan – Oct 22, 2024 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, proudly announces the launch of its industry-leading functional safety RISC-V processor AndesCore™ D45-SE, targeting ISO 26262 ASIL-D (Automotive Safety Integrity Level D) certification.
The D45-SE, derived from the production-proven D45, is a 32-bit, 8-stage dual-issue processor that supports the RISC-V GCBP extensions, including single/double precision FPU, 16-bit compression, bit manipulation, draft of packed SIMD/DSP extensions, and the Andes performance enhancements. Furthermore, it incorporates numerous safety features, such as dual-core lockstep (DCLS), a real-time diagnostic safety circuit that utilizes an additional processor and a set of comparators to enhance the diagnostic coverage; ECC for memory soft error protection; bus protection to secure bus transactions; a core trap status bus interface that provides real-time trap status information from the core; and StakSafe™, a hardware mechanism that protects the stack, and maintains the same outstanding 6.12 Coremark/MHz as the D45. With these safety enhancements, the D45-SE ensures fault tolerance that meets the rigorous demands of safety-critical applications.
Additionally, it supports split-mode, allowing two cores to run independently when split-lock is configured. The processor also offers comprehensive safety documentation and support to facilitate ISO 26262 compliance, assisting customers in integrating safety features into their designs. The D45-SE marks a milestone, underscoring Andes’ commitment to providing industry -leading, mission-critical solutions for the automotive industry and beyond.
“We are thrilled to announce the D45-SE, a high-performance RISC-V processor engineered to deliver exceptional safety and reliability. It is a testament to our dedication to delivering safe and reliable solutions,” said Frankwell Lin, Andes Chairman and CEO. “This accomplishment reflects our ongoing commitment to supporting the automotive industry’s drive towards higher safety standards and innovation.”
About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.For more information, please visit https://www.andestech.com/en/homepage
|
Andes Technology Corp. Hot IP
Related News
- Andes Technology Unveils Andes D23 and N225 Cores Pioneering the Next Generation of Compact, Performant, and Secure RISC-V Processor Technology
- Safety element for automobiles, production or health can be implemented on the own microcontroller chip: RISC-V processor AIRISC-SAFETY from Fraunhofer Institute for Microelectronic Circuits and Systems IMS
- Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios
- Andes Technology Unveils the AndesCore™ D23, a Feature-Rich, Low-Power and Highly-Secured Entry-Level RISC-V Processor
- Andes Technology Unveils The AndesCore® AX60 Series, An Out-Of-Order Superscalar Multicore RISC-V Processor Family
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |