TSMC drives A16, 3D process technology
By Nick Flaherty, eeNews Europe (November 20, 2024)
TSMC is looking to introduce its A16 1.6nm process by the end of 2026 with an IEEE standard for its 3Dblox technology.
The Open Innovation Platform (OIP) meeting in the Netherlands this week showed that the 2nm process will be in production in 2025 following early tapeouts this year, with a variant called N2P nanoFlex with the option for short standard cells for smaller area and greater power efficiency or tall cells for more performance.
This will give a 12% boost in energy efficiency over the base 2nm process, while A16 will give a 30% boost with the same density as N2 nanoFlex. Both TSMC and Intel are detailing their 2nm technologies at the IEDM conference in December.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- TSMC's A16 Process Moves Goalposts in Tech-Leadership Game
- Synopsys DesignWare PVT Subsystem Drives Performance, Power and Silicon Lifecycle Management on TSMC's N3 Process Technology
- Moortec Drives Optimised Performance & Increased Device Reliability on TSMC's N5 and N5P Process Technologies with its Complete In-Chip Monitoring Subsystem
- Altera and TSMC Jointly Develop World's First Heterogeneous 3D IC Test Vehicle Using CoWoS Process
- TSMC goes it alone with 3-D IC process
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset