Fujitsu pushes SiP over SoC for fast-cycle RAM

Fujitsu pushes SiP over SoC for fast-cycle RAM
By Paul Kallender, EE Times
July 12, 2001 (5:01 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010712S0063

TOKYO — Eschewing a more costly system-on-chip (SoC) strategy for its fast-cycle RAM (FC-RAM) parts, Fujitsu Ltd. is heavily backing system-in-package (SiP) technologies as a cheaper, faster method to design and ship memory for mobile and networking applications.

Masao Nakano, director of application engineering at Fujitsu's memory system LSI division, said he plans to roll out a series of SiPs that will bring FC-RAM densities as high as 128 Mbits running on voltages as low as 1.8 V over the next two years.

Fujitsu released two SiP-housed 64-Mbit FC-RAMs this week, each with an SDRAM interface, running at 2.5 V on the company's 0.2-micron process. These parts featured a 64-bit bus width, a bandwidth of 648 Mbytes/second and an 81-MHz clock frequency suitable for image-processing equipment. This is just the beginning, Nakano said.

In three months, he said, the company will release a 32-Mbit version. A year from now Fujitsu plans to rele ase a 48-Mbit part consisting of a 16-Mbit and 32-Mbit chip. By the end of next year, the company will shrink the process technology to 0.18-micron.

While doing that, Fujitsu will boost its FC-RAM technology, particularly improving addressing control and developing smaller array segmentation. Combined, these strategies will dramatically reduce power consumption, Nakano said. Fujitsu has targeted that power consumption at 100 milliwatts when running at 108 MHz, and supply voltage down to 1.8 volts, said Nakano.

According to the company's SiP road map, Fujitsu will roll out a 16-Mbit version next year, a new 64-Mbit running on 1.8 volts late next year and 128-Mbit-density parts running on 1.8 V in the middle of 2003.

The company is also investigating a very-high-bandwidth version with a double-data-rate (DDR) interface for 0C-768 applications that will operate at 300 MHz, said Takenori Jinno, the director for electronic devices in Fujitsu Ltd.'s business promotion division.

"That's about fi ve years from now, when the customer needs them," Jinno said.

Meanwhile, said Jinno, the company is developing DDR interfaces, hoping to take a slice out of application-specific memories for fast graphics, networking and supercomputers next year.

Nakano said SiP became clearly preferable to developing more complicated SoC technology, at least for a relatively expensive but high-performance memory technology such as FC-RAM. For the 64-Mbit parts just released, Fujitsu said, developing an SoC would have delivered a "huge chip," about 15 mm². The SiP measured 10 mm², said Nakano. An SoC would also have drawn about one third more power, he said.

"Other makers may prefer to develop SoC, but . . . SoCs cost more and take more time to develop and are more expensive. For low-density SRAM, SoC might be OK. But when you go to high-density memories, if you consider the small size, the low power needs and the flexibility, SiP has to be the best solution," said Nakano.

A flip-chi p approach is also in the works, said Nakano, with Fujitsu developing bump technology "within the next two years," he said.

Timing will depend mainly on when the company feels able to invest in this new technology, Jinno said. "Wire bonding has a comparatively cheap running cost and uses currently installed equipment. For flip chips, we need new machinery, factories and technology, and that costs a lot," he said.