Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY

Copenhagen, January 14, 2025 – Chip Interfaces, a leading provider of high-performance chip-to-chip interface IP cores, is pleased to announce the successful completion of the interoperability test between its Interlaken IP core and Cadence’s 112G Long-Reach SerDes PHY. This milestone marks a significant achievement in ensuring seamless integration and reliable data transfer between the two technologies for applications ranging from data centers, enterprise networks, and wireless infrastructure to industrial, automotive, and avionics networks.

The Interlaken IP core, known for its scalability and high-bandwidth performance, supports up to 2.6 Tbps total bandwidth by means of 48 lanes of up to 56Gbps NRZ, or with 4:1 with PMA attachment, 24 Lanes of up to 112Gbps PAM4 SerDes rates per lane. This highly optimized silicon and PHY-agnostic implementation of the Interlaken Protocol version 1.2 is designed for both ASICs and FPGAs, making it a versatile solution for various applications. This shows the flexibility of the Cadence 112G Long Reach SerDes PHY to seamlessly work with Ethernet and non-Ethernet PCS/MAC protocol solutions.

The interoperability test was conducted to validate the compatibility and performance of the Interlaken IP core with Cadence’s 112G Long-Reach SerDes PHY. The successful completion of this test demonstrates the robustness and reliability of the Interlaken core as well as the complete subsystem solution in real-world scenarios, ensuring that customers can confidently deploy these technologies in their systems.

The Interlaken IP core’s key features include combined TX and RX data paths with PCS, MAC & Protocol layers, robust error detection and correction mechanisms based on RSFEC. These features, combined with the successful interoperability test, position the Interlaken IP core as a leading solution for high-speed chip-to-chip communication.

For more information about the Interlaken IP core and its capabilities, please reach out to sales@chipinterfaces.com or visit www.chipinterfaces.com

About Chip Interfaces

Chip Interfaces is a leading provider of high-performance digital IP cores, designed to meet the rigorous demands of next-generation applications. The extensive interface IP portfolio includes JESD204, MIPI, Interlaken, CPRI/eCPRI, and RSFECs, all of which are silicon-agnostic and customizable.

At Chip Interfaces we are dedicated to our commitment to innovation, ensuring our IP cores are interoperability tested with top PHY providers, verified using the latest UVM regression techniques, and validated in test beds. This rigorous process guarantees seamless integration, simplifies design, and minimizes integration risks.

Our commitment to quality and excellence, combined with our genuine desire to see our customers succeed, makes us a trusted partner for every project.