Accellera Announces IEEE Standard 1801™-2024 is Available Through IEEE GET Program

Elk Grove, Calif. -- March 19, 2025 -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that the recently published IEEE Std. 1801™-2024 Unified Power Format (UPF) 4.0 Standard, which specifies and verifies low-power intent, is now available for download fee-free, courtesy of Accellera as part of the IEEE GET Program.

“Our collaboration with the IEEE Standards Association empowers design and verification engineers worldwide with fee-free access to leading-edge standards,” stated Lu Dai, Accellera Chair. “By providing IEEE Standard 1801™ through the GET Program, we offer designers a valuable resource to explore, craft, verify, and apply power-aware concepts to electronic systems and deliver power-aware silicon IP. This accelerates learning and adoption, fostering a global community with a shared foundation of knowledge and best practices.”

IEEE Standard 1801, also known as Unified Power Format (UPF), is a standardized specification language designed to define the low-power architecture of an ASIC. It streamlines integration throughout the entire verification and implementation process. Built on Tool Command Language (TCL), UPF complements existing hardware description languages such as SystemVerilog and VHDL. It allows designers to specify essential power management elements such as power domains, supply networks, power shutoff, and multi-voltage designs.

UPF plays a crucial role in modeling low-power architectures during simulation, guiding implementation in synthesis and place-and-route, and ensuring that the final design is both logically and electrically correct. As a fundamental technology for reducing power consumption, UPF is widely adopted across all sectors of the semiconductor industry. Its comprehensive approach ensures that low-power designs are accurately represented and efficiently implemented, making it indispensable in modern ASIC development.

“The IEEE Standard 1801-2024 version introduces several significant innovations to keep pace with the rapidly evolving low-power design and verification methodologies,” stated John Decker, IEEE P1801 Working Group Chair. “Innovations such as supply net tunneling and Value Conversion Method (VCM) create new interfaces between analog/mixed-signal and the digital design spaces. Major extensions to the retention specification enable precise modeling of the most advanced state retention cells. Additionally, the introduction of refinable macros supports new IP methodologies, allowing in-context optimizations while preserving IP verification efforts. Overall, this revision includes over 65 topics implemented by the working group, representing a broad spectrum of productivity, verification, and low-power design enhancements that will benefit the low-power design community.”

Other key new features to the standard include:

• Virtual supply and supply sets
• Improved successive refinement methodology with implementation UPF
• Clarification of precedence rules
• Updates on object naming, especially escape and generate block names
• Introduction of abstract power source
• UPF library

The IEEE Standards Association has established an open-source community space within the IEEE 1801-2024 repository, accessible in IEEE SA Open. This platform allows users to share comments, provide feedback, and contribute examples, fostering collaboration and enhancing the standard. The repository currently contains examples from Annex E and the UPF library. Annex E provides practical examples that demonstrate the application of UPF in real-world scenarios, helping users understand how to implement low-power design techniques effectively. The UPF library contains a collection of reusable components and templates that can be used to streamline the design and verification process. By leveraging these resources, users can accelerate their learning and adoption of UPF, contribute their own examples, and collaborate with others in the community to build a robust repository of best practices and innovative solutions.

The IEEE GET Program - Design Automation Standards was established to provide pre-paid access of selected standards to engineers and designers worldwide at no cost. The program helps expand the global reach of technical knowledge developed by industry, accelerates standards adoption, and contributes to an open knowledge community and the fostering of innovation. As a partner in the GET Program since its inception, Accellera has sponsored more than 200,000 downloads of Accellera-developed standards. For a list of Accellera standards and Accellera-sponsored IEEE standards available for download at no cost, visit the Accellera Downloads page.

About Accellera Systems Initiative

Accellera Systems Initiative is an independent, not-for profit organization dedicated to creating, supporting, promoting and advancing system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit accellera.org. Find out more about membership.

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