2025 RISC-V CON: Andes Technology Celebrates 20 Years, Bringing Together Innovators, Engineers, and Ecosystem Leaders
San Jose, CA – April 4, 2025 – Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, proudly announces the Silicon Valley 2025 Andes RISC-V CON scheduled for April 29, 2025. The in-person event will gather industry leaders, innovators, and developers to explore the latest advancements in RISC-V technology and celebrate Andes Technology’s two decades of groundbreaking innovation.
Attendees will have the opportunity to gain exclusive insights from Andes executives and prominent industry leaders, explore the latest advancements in RISC-V technology, and learn about cutting-edge projects shaping the RISC-V future. Additionally, engage and network with Andes and its valued ecosystem partners, fostering collaboration and knowledge exchange.
The 2025 RISC-V CON will feature two parallel conference tracks: The Main Conference and Exhibition, open to everyone, and the new Developer Track, designed for engineers seeking deep-dive, hands-on technical training.
For more details and to register, visit the event website
Main Conference and Exhibition
The main conference welcomes all attendees, featuring over ten sessions and speeches that cover the RISC-V market and the development of SoCs using RISC-V across AI, automotive, application processing, communications, and more. Participants will also have opportunities to network with speakers and exhibitors from over twenty sponsoring companies offering IP, software, tools, services, and products.
Highlighted Main Conference Presentations:
- Frankwell Lin, Chairman and CEO, Andes Technology – Celebrating 20 years of driving SIP innovation and 15 years of pioneering RISC-V.
- Dr. Charlie Su, President and CTO, Andes Technology – Provides insights on advancing modern computing with Andes RISC-V processor solutions.
- Paul Master, Co-founder and CTO, Cornami – Presenting Fully Homomorphic Encryption, the Holy Grail.
- Fireside chat: What’s coming in AI? – Facilitated by Charlie Cheng, Andes, Board Advisor with keynotes from:
- Jeff Bier, Founder, Edge AI and Embedded Vision Alliance
- Pete Warden, Founder & CEO, Useful Sensors
Developer Track – Hands-on Technical Training (Limited Seating!)
For engineers looking to gain practical insights, the Developer Track offers four in-depth sessions designed to provide hands-on experience with cutting-edge RISC-V concepts and system optimization. Attendees should bring a fully charged laptop.
- Optimization with RISC-V Vector ISA – Understand how RISC-V Vector Extensions (RVV) enhance performance and get hands-on experience using AndeSight tools.
- IAR Professional Tools for RISC-V – Discover how advanced debugging and functional safety tools accelerate development cycles.
- Create Your Own RISC-V Custom Instructions – Learn to enhance RISC-V ISA with Andes’ Automated Custom Extensions (ACE) and experience hands-on instruction with Andes Copilot.
- Unleashing the Power of Heterogeneous Computing: Optimizing Resource Utilization – Join Andes, Imagination, and Baya to explore how trace-based CPU and GPU analysis can boost compute efficiency.
Event Details:
Location: DoubleTree by Hilton, San Jose, CA (Free Parking)
Time: 8:30 - 6:00 PDT
Admission: RISC-V CON is free to attend
Registration: visit the event website
|
Andes Technology Corp. Hot IP
Related News
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- X-Silicon Introduces the World's First Vulkan Driver Implementation for RISC-V, Enabling an entire Ecosystem of 3D Graphics, AI and Compute for Low-Power, Mobile, Edge and IOT Devices
- Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel
- Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem
- TASKING, Andes, and MachineWare Team Up to Facilitate Rapid Development of RISC-V ASIL Compliant Automotive Silicon
Breaking News
- Arteris Wins Two Gold and One Silver Stevie® Awards in the 2025 American Business Awards®
- Faraday Adds QuickLogic eFPGA to FlashKit‑22RRAM SoC for IoT Edge
- Xylon Introduces Xylon ISP Studio
- Crypto Quantique announces QRoot Lite - a lightweight and configurable root-of-trust IP for resource-constrained IoT devices
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
Most Popular
- Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
- Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions
- M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |