Silicon Proven AV1 Decoder IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT

April 24, 2025 -- Allegro DVT, the leading provider of video processing silicon IPs and video compliance streams, has announced that its D310 AV1 decoder silicon IP is silicon proven having been integrated into SoCs designed into various advanced silicon processes down to 3nm.

Allegro DVT’s D310 IP is part of the D300 series highly customizable silicon IP family that builds on a scalable architecture allowing picture resolutions ranging from HD/4K up to 8K/16K while providing support for sample sizes from 8-bit to 12-bit and chroma subsampling from 4:0:0 up to 4:4:4.

Allegro DVT is able to address the growing demand of state-of-the-art video processing blocks in advanced System-on-Chips (SoCs) by providing highly configurable decoding IP core supporting a variety of selectable codecs. In addition to AV1, the D300 series also supports JPEG, H.264, HEVC, VP9 and VVC video formats. Furthermore, Allegro DVT’s unique and scalable architecture approach offers the best trade-off between silicon size and power consumption and keeps the operating frequency of the resulting 8K solutions at a reasonable level to allow physical implementations in mainstream and cost-efficient process node technologies.

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