Jury still out for EDA industry on structured ASICs

Some believe that ASIC makers will use the structured ASIC to exact a quiet revenge on EDA vendors, competing directly with them in design services and intellectual-property (IP) libraries as well as tools. To maintain the full value of the structured-ASIC proposition over high-end FPGAs, this camp argues, ASIC vendors will have to keep tool prices low or even give to ols away, much as Altera and Xilinx do in the programmable-logic space.

Yet EDA executives along with Gary Smith, chief EDA analyst with Gartner Dataquest, point to a different scenario. As in the mid-'80s with custom designs, this camp maintains, ASIC vendors will build and maintain control over much of the structured-ASIC tool flow for a few years. But as the market matures, they will relinquish some control and rely more on commercial EDA, in deference to users' desire for silicon-independent tools that allow them to target their designs to the lowest-priced, highest-performance chip vendor.

"I think we are going through a new silicon and a new tool restructuring, much in the same way we did in the early '90s," said Alain Labat, president and chief executive officer of Tera Systems Inc., whose tools ensure that a design's register-transfer-level (RTL) code can be easily implemented in a structured-ASIC process.

Structured ASICs are seen as breathing new life into the old ASIC model , in which customers designed through synthesis, then threw their design over the wall to an ASIC vendor. Structured-ASIC vendors promise faster turnaround because users typically configure only three to 12 of the chip's top metal layers, out of two dozen or so total. The rest of the layers are pre-implemented by the silicon vendors and the wafers warehoused until a customer comes along to tailor the final product.

Vendors promise that the entire chip development cycle, from concept to production silicon, will take eight months or less. NEC Electronics Inc., one of the first to get its structured-ASIC process online, has reportedly pumped out 30 designs in six months.

The structured-ASIC vendors have reclaimed the tool methodologies, much of the tool flow and even tool production from commercial EDA vendors, ensuring that their tools are correlated to silicon and guardbanding so that users can easily design to the new fabrics. Lightspeed Semiconductor's flow, for example, doesn't require any third-party tools, and users of LSI Logic Corp.'s RapidChip need buy only two tools to use LSI's flow.

For Rapid Chip users, that amounts to roughly $30,000 worth of EDA tools-a far cry from the hundreds of thousands of dollars companies must spend on tools to design a standard ASIC or system-on-chip, or to implement COT (customer-owned tooling)-to-foundry flows.

None of this bodes well for the majority of EDA vendors, especially if the structured-ASIC market starts stealing business from the high-end ASIC and COT-to-foundry markets, where the bulk of the EDA industry's revenues come from today.

Few tools as yet

A few EDA vendors are developing tools to serve this emerging market. Expanding its horizons beyond its bread-and-butter FPGA tools, Synplicity Inc. was quick to offer logic synthesis and physical synthesis tools for structured ASICs. For the last two years Synplicity has been trying with little success to take standard-cell ASIC synthesis seats away from Synops ys Inc. The company sees its early entry into the structured-ASIC market as a way to capitalize on a nascent business while also winning favor with ASIC vendors and users as it attacks Synopsys in the high end.

Magma Design Automation, which has been trying to take market share from Cadence and Synopsys in the RTL-to-GDSII tool flow, earlier this month purchased PLD synthesis startup Aplus Design Technologies Inc., signaling an intent to jump into the structured-ASIC market (see June 16, page 8).

But the larger EDA vendors have been in no rush to offer tools. Mentor Graphics Corp. chairman and CEO Wally Rhines said his company's existing tools could be adjusted to work with structured ASICs if that market does take off. So far, neither Synopsys nor Cadence Design Systems Inc. has announced product road maps for this market, but both said they are monitoring it. Officials at the two companies, however, said they don't see structured ASICs as a threat to their business.

John Gallagher, vice president of ASIC tools at Synplicity, said he doesn't think Cadence or Synopsys will be big players in structured ASICs because each structured-ASIC vendor has its own fabric, and an EDA vendor would have to customize its tools to a particular vendor's process in order to add something significant to the flow.

Old-time ASIC vendors, for their part, seem content working with smaller EDA vendors, especially since many of the large suppliers are essentially competitors. Now offering design services, cores and all-in-one RTL-to-GDSII flows, EDA companies have pushed back the design handoff point to placement or further, which has cut down or eliminated the services charges ASIC vendors used to gain from customers.

LSI Logic's RapidChip methodology and tool flow illustrate how structured-ASIC vendors are trying to roll back the clock to the glory days of the ASIC business. The tools, called RapidWorx, only require two third-party offerings, both specific to LSI Logic's process: TeraForm Rapi dChip from Tera Systems and AmplifyASIC RapidChip from Synplicity.

Users work with LSI Logic's front-end cockpit tool, called RapidBuilder, to plan a design. They select large, preconfigured IP blocks, add soft cores from LSI's core library, assign clocks and memories, and write RTL logic blocks. TeraForm checks the RTL to ensure it will work in a RapidChip. Logic synthesis and physical synthesis are performed with Amplify, which also optimizes a gate netlist. Users then hand off the optimized netlist, placement DEF file and RapidBuilder database to LSI Logic, which places and routes the design, and cranks out a chip a couple of months later.

EDA vendors believe that as the category evolves, structured-ASIC architectures will have to be built with high-end, high-priced standard-cell commercial EDA tools. They point out that after a customer hands off a design to a structured-ASIC maker, the chip manufacturer still needs to perform physical design and analysis. However, the price points of tho se tools would seemingly be far below those of standard-cell ASIC tools, simply because there are fewer layers to place and route.

Tom Ferry, vice president at Synopsys' IC implementation group, said the big vendors have a leg up in that standard-cell customers are familiar with their tools and may be reluctant to be tied down to using one structured-ASIC vendor's tool set.