Sagantec says tool finds errors others miss

Sagantec says tool finds errors others miss
By Michael Santarini, EE Times
January 28, 2002 (3:38 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020128S0050

SAN MATEO, Calif. — Sagantec — best known for its IC process migration software — has released a new class of physical verification tool that automatically finds and, more importantly, fixes errors that may or may not be caught during the design-rule checking (DRC) and layout vs. schematic (LVS) stages of physical verification.

The tool, SiFix, was created in response to user requests to allow physical designers cutting their teeth on leading-edge processes to find and fix errors after the routing of the full-custom design process, said Coby Zelnik, senior vice president of business development at Sagantec (Fremont, Calif.).

"Advanced silicon processes of 0.13 micron and below present a number of errors that current methodologies and tools such as DRC and LVS tools can't yet fix," Zelnik said. "SiFix will find errors detected by DRC and LVS tools and many that won't be detected by those tools and will automatically fix them."

He noted that a DRC tool, for example, could identify locations that violate forbidden gap rules on gate-gate spacing, but it cannot implement design changes to solve the problem, whereas SiFix can.

He said LVS and DRC tend to be pass or fail tools, determining whether a distance between wires is respected. In deep submicron, the manufacturability model now includes a gray area that allows for certain, very small feature distances in critical parts of the design. The new tool, Zelnik said, can implement and verify this type of manufacturability assessment.

Zelnik noted that because the tool finds and fixes problems introduced by routers or not detected by LVS and DRC, it actually helps yield, in a roundabout way. "Yield is a subject that has not really trickled down to the EDA industry yet," Zelnik said. "But with new processes coming online and finer geometries, tools are going to have to be more aware of yield issues" in the electronic design automation field.

Zelnik said the SiFix tool accep ts GDSII or files in Cadence database format and will soon accept LEF/DEF files for cell-based design. Users then create a technology rules file, specifying areas in the design and violations they would like the tool to find and fix. "It is very similar to a technology file that users would complete when using a DRC tool," Zelnik said, noting users can specify, for example, that they only want a particular check and fix to be run on a specific metal layer.

After setting up the constraints, users push a button and the tool then finds cases where conditions are not met, and it automatically fixes them. Zelnik said that the tool will only check and fix localized errors. "This tool, once it finds problems, limits the fix to the minimum adjustment needed to correct an error," Zelnik said. "If the tool finds an error and adds a via for example, it may slightly push a net to the side, but nothing else in the design will change."

No big changes

The tool will not, however, make any big changes that will affect the rest of the design. Zelnik said the tool typically finds 10,000 small errors and fixes them. "It will perform via doubling or widen segments of wires if stronger currents are need in particular parts of a design," he said. "It will also fill in notches that routing tools introduce to layouts implemented in new processes. This is a pain for many users because it requires them to go back and fill in the notches manually after the routing process. SiFix will fix these automatically.

"The tool will also implement Halation design rules that DRC and LVS tools cannot. DRC and LVS tools are black and white in terms of wire spacing," Zelnik said. "Some processes can permit wires in particular areas of a design to be closer together. We can do this."

The tool can also implement conditional or context-dependent rules, such as the ratio of contacts to gates and via spacing.

The tool produces a report that lists all the errors it has located and fixed by category and also the location of those problems. Zelnik said if it locates a problem that requires a large adjustment, SiFix does not implement a fix but reports it to the user, who can make the change manually. These larger fixes would likely require a change implemented with a router or with a process migration tool.

Zelnik said that the tool does not replace sign-off DRC and LVS, but because it hasn't altered essential elements of the design, timing does not have to be checked again.

The tool is vendor-neutral and can be used with any tool that inputs and outputs GDSII, Zelnik noted.

He said the tool is currently being used by full-custom digital, analog and mixed-signal design groups implementing designs in the newest silicon processes, but said the tool could come in very handy for ASIC designers on the leading edge. The company claims the tool in hours can find and fix errors that would normally take designers weeks to fix manually.

SiFix is available now under time-based licensing starting at $225,000 a year. SiFix i s available on Solaris, HP-UX and Linux platforms.