Startup stakes out ground between FPGAs and ASICs

Startup stakes out ground between FPGAs and ASICs
By Anthony Cataldo, EE Times
July 9, 2001 (3:39 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010709S0075

SAN MATEO, Calif. — Startup eASIC Corp. will port its mask-programmable configurable logic core this year to Taiwan Semiconductor Manufacturing Co. Ltd.'s 0.13-micron process technology as it looks to find its place between standard cell ASICs and programmable logic devices, said Zvi Or-Bach, president and chief executive officer of eASIC.

By tapping the latest process design rules, eASIC said, it can pack as many as 60,000 logic gates onto 1 mm² of silicon using a cell architecture that's loosely based on an FPGA but that is some 20 times denser.

eASIC (San Jose, Calif.) expects to tape out its first devices based on the new TSMC process by September or October, said Or-Bach, the company's founder.

Though eASIC's underlying logic cells are similar to those in FPGAs, the company has shifted routing from the lower diffusion layers to the top four metal layers. A block is programmed by making a via mask change on the sixth lay er of an eight-metal-layer design.

In this way, eASIC has stripped the programmable interconnect that accounts for most of the bulk in FPGA logic cells. That also improves speed because signals are mostly racing along the higher metal-interconnect levels rather than having to negotiate the lower diffusion wires. At 0.13-micron process rules, eASIC promises clock rates of 700 MHz, almost five times faster than FPGAs and 100 MHz short of standard cell designs.

eASIC also strayed from standard FPGAs by using three-input lookup tables, with one of the inputs connected to a NAND gate. That was done to improve logic-cell density while providing similar functionality as a four-input lookup table, Or-Bach said.

The logic blocks can also be configured as SRAM or as a full-fledged programmable logic device that is bit stream programmable. In the latter case, though, the logic density would fall to 20,000 to 30,000 gates/mm², the company said. As such, field programmability will be used sparingl y, such as for downloading new encryption coefficients, Or-Bach said.

Designer target

But eASIC is trying to woo not FPGA customers who want post-production modifications made to the silicon but ASIC designers more interested in programming once and moving into volume production. "This is not an FPGA," Or-Bach said. "If you want 1 million gates of field programmability, we are not the solution."

The company, however, will find itself competing against FPGA companies looking to add bits of programmable logic to system-on-chip designs. Among them are Adaptive Silicon Inc., Actel Corp. and possibly Xilinx Inc., which recently said it was considering licensing programmable gate array blocks to ASIC companies. LSI Logic Corp., for one, has been working with Ericsson on a DSP-based broadband processor with a 40-MHz accelerator based on Adaptive's embedded programmable logic architecture.

Though eASIC's approach to programming falls outside of the scope of traditional FPGAs, there is evi dence that some level of mask programmability is being embraced by Altera Corp., a leading programmable logic vendor. In September, the company plans to unveil its Hard Copy family of mask-programmable devices, which will reduce the cost of programmable logic devices for mid- and high-volume production, an Altera spokesman said. Archrival Xilinx, however, has scoffed at this approach.

Industry observers have pointed out that mixing high-density standard cells with programmable logic can limit speed and severely affect die area. eASIC is making the case that, with some trade-offs, there is a way to get some programmability while mollifying the handicaps of FPGAs.

"Embedded FPGAs still have some fundamental issues," Or-Bach said. "It has to be less than 10 percent of the die if you want to embed [FPGA]."