MIPS Technologies MIPS32 4Km Core Selected As Standard By THALES Communications For Low-Power, High-Performance Security Access Devices
MIPS Technologies MIPS32 4Km Core Selected As Standard By THALES Communications For Low-Power, High-Performance Security Access Devices
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--June 28, 2001-- MIPS Technologies, Inc. (Nasdaq:MIPS; Nasdaq:MIPSB - ), a leading provider of industry standard processor architectures and cores for digital consumer and network applications, today announced that THALES Communications (formerly Thomson-CSF Communications) has taken a license for the 32-bit MIPS32(TM) 4Km(TM) processor core for low-power, high-performance security access devices. THALES Communications, one of the world's leading suppliers of electronics for defense and professional applications in information and communications systems, will be using the core in ASICs (application specific integrated circuits) for security applications.
``We benchmarked cores from most of the leading suppliers of embedded processor cores,'' said Bernard Candaele, ASIC & EDA department manager at THALES Communications. ``The 4Km core evaluation results fulfilled our needs for a high-performance core to run the security algorithms. Normally, a coprocessor core would be required as well as a core to process the intensive calculations that the algorithms require, but this 32-bit core is powerful enough on its own. No coprocessor means that the ASIC is smaller, less expensive to make and runs on less power. Low power consumption is a clear advantage of the MIPS core.
``The other critical factor was that the MIPS architecture is configurable. We can select our own parameters to enhance the performance for this security application, while still being compliant with the MIPS architecture specifications. Because of the security aspects of the application, we can keep these enhancements totally in-house without affecting our ability to use the vast wealth of third party tools that are available for working with the MIPS architecture such as compilers and debuggers.''
The SoC (System on Chip) Excellence Centre of THALES Communications intends to standardize on the MIPS architecture and use it for other applications such as wireless, networking and security.
John Hall, Vice President of MIPS Technologies' European Operations, commented, ``This is a significant win for MIPS Technologies and the French team, as it is the second license deal to be signed with a French company; the first being Gemplus, which was for a high-performance, low-power smartcard application. THALES Communications is highly respected in France and for it to choose MIPS Technologies as a standard will open the door for other French companies to follow suit. We recently opened our French offices so that we can provide the local sales and support that are so important for companies when they commit to an embedded processor architecture.''
About THALES Communications
THALES Communications is a subsidiary of THALES, a group ranking among the top European companies and the world leader in professional electronics on three business segments: Defense, Aeronautics, Information Technology and Services.
As a designer, prime contractor, integrator and value-added service provider, THALES Communications is the architect of the defense communications and information systems needed by customers to meet all the operational needs of their land, air and naval forces. This comprehensive approach is the key to effective tri-service integration and allied interoperability in the field.
Since the acquisition of the British company Racal Electronics, THALES Communications has become the world leader in defense communications, a market that is growing after the civil communications market, with a few years delay.
Present in 14 countries, THALES Communications achieves a turnover around 1.5 billion euros and employs 9,000 persons over the world. www.thales-communications.com
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and network applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at 650/567-5000 or www.mips.com.
Note to Editors: MIPS® is a registered trademark in the United States and one or more other countries, and MIPS32(TM) and 4Km(TM) are trademarks of MIPS Technologies, Inc. All other trademarks referred to herein are the property of their respective owners.
Contact:
MIPS Technologies, Inc.
Gerry Ziegler, 650/567-5059
zig@mips.com
or
The Hoffman Agency (for U.S. press)
Gustavo Santoyo, 408/286-2611
gsantoyo@hoffman.com
or
Vortex Public Relations (for European press)
Nigel Robson, +44 1481 233080
nigel@vortexpr.com
Related News
- MIPS Technologies MIPS32 4Km Core Selected As Standard By THALES Communications For Low-Power, High-Performance Security Access Devices
- ARM Selected To Deliver Low-Power and High-Performance Libraries For IBM, Chartered and Samsung 45-Nanometer Common Platform Technology
- NEC Electronics America Uses Cadence Encounter for High-performance, Low-power ARM11 Processor
- Fujitsu Develops Technology for Low-Power, High-Performance 45nm Logic Chips
- SiCortex Inc. Licenses MIPS64 Architecture for Low-power, High-performance Teraflop Computing
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |