Virage Logic extends its reach in Asia with Silterra IP license agreement
Companies to Deliver Highly Optimized Semiconductor IP for Cost-Effective, High Yielding SoCs
FREMONT, Calif. and KULIM, Malaysia, July 24, 2003 - Virage Logic (Nasdaq:VIRL), a leading provider of best-in-class semiconductor IP platforms, and Silterra Malaysia Sdn. Bhd., a premier semiconductor-manufacturing foundry, today announced that Virage Logic has licensed its Technology-Optimized semiconductor IP Platform to Silterra for the foundry's advanced 0.18-micron CL180G process and its embedded memory for the foundry's 0.25-micron CL250G process. The agreement provides chip designers utilizing Silterra's technologies with enhanced performance and accuracy for designs containing embedded memory, logic libraries and I/O cells from a single source.
"Building on our IP initiative, the partnership with Virage Logic enables us to deliver not only silicon-proven IP, but a design platform that is highly optimized for our customer's specific needs. As designs become more complex, customers are demanding quality design and manufacturing solutions. We want to be their vendor of choice," said Victor Kwong, vice president of design solutions, Silterra. "Virage Logic is long known to deliver reliable, high- performing IP. We are pleased to bring that expertise and quality to our customers."
Under the terms of the agreement, Virage Logic will deliver its Technology-Optimized Platform – comprising of silicon-proven embedded memories, logic and I/Os – for Silterra's 0.18-micron logic process. In addition, Virage Logic will deliver its Area, Speed and Power (ASAP) MemoryTM product line for Silterra's 0.25-micron logic process. The companies' relationship will enable customers to gain access to Virage Logic's offerings that provide enhanced reliability and manufacturability. With Virage Logic's extensive quality assurance efforts through its FirstPass-SiliconTM Characterization Program, Silterra will have IP that is not only reliable and manufacturable, but will perform to specification. Virage Logic's FirstPass-Silicon Characterization Program provides an industry benchmark in quality, reliability and completeness.
"As the market moves to an outsourcing model, we are extending our compatibility to all the major foundries around the world. Silterra's strength and success in major global markets, especially in Asia, are key as we continue to build our presence in that region," said Adam Kablanian, president and CEO, Virage Logic. "Silterra's advanced processes, combined with our Technology-Optimized Platform, provide our customers with a distinct advantage as they develop designs in today's and next-generation technologies. We look forward to working with Silterra in delivering cost-efficient, high-performing and reliable chips for a broad range of applications."
Technology-Optimized Semiconductor IP Platforms
Building on its technology and market leadership position, Virage Logic's Technology-Optimized Platforms aim to meet the critical requirements of reducing silicon costs and failure risks, while boosting performance and ensuring high manufacturing yields for a particular foundry or Integrated Device Manufacturer (IDM) process. By providing silicon-proven, integrated IP that is compatible with all the major EDA flows, Virage Logic's Technology-Optimized Platforms address the needs of complex and mainstream System-on-Chip (SoC) designs.
Virage Logic's Technology-Optimized Platforms are based on its highly differentiated IP including the Self-Test and Repair (STAR) Memory SystemTM, the ASAP Memory product line, the ASAP LogicTM standard cell libraries, and the recently introduced Base I/O libraries. Technology-Optimized Platforms enable customers to expedite the creation of next-generation products by addressing the increasingly complex task of identifying and obtaining the semiconductor IP needed to produce successful, on-time products. Virage Logic's semiconductor IP platform strategy calls for the delivery of Technology-Optimized Platforms for a broad range of third-party foundry and IDM processes.
Availability
The CL180G libraries are available now and the CL250G libraries will be available in Q3 2003. Availability of the libraries on other processes will be based on customer demand. About Silterra Malaysia Sdn. Bhd.
Silterra Malaysia Sdn. Bhd. is a premier semiconductor wafer foundry offering customers major foundry compatible 0.25µm, 0.22µm and 0.18µm CMOS logic, high-voltage and mixed-signal/RF technologies. The company was a winner of Semiconductor International's 2002 Top Fab Award. Silterra's wafer fab will reach its planned capacity of 40,000 eight-inch wafers per month in 2004. The company's headquarters and factory are located in Kulim, Malaysia, and has sales and marketing offices in Sunnyvale, California and Hsinchu, Taiwan. For additional information on Silterra or its services, please visit www.silterra.com.
About Virage Logic
Virage Logic Corp. (Nasdaq:VIRL) is a leading provider of best-in-class semiconductor IP platforms based on memory, logic, I/Os, and IP development tools that are silicon proven and production ready. Virage Logic meets market demands for cost reduction, while improving performance and reliability for fabless and integrated device manufacturer (IDM) companies focused on the consumer, communications and networking, handheld and portable, and computer and graphics markets. Virage Logic is headquartered in Fremont, California and has sales and support offices worldwide. For more information, visit www.viragelogic.com or call (877) 360-6690 toll free or (510) 360-8000.
###
SAFE HARBOR STATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE SECURITIES LITIGATION REFORM ACT OF 1995:
Statements made in this news release other than statements of historical fact are forward-looking statements, including, for example, statements relating to Virage Logic's business outlook, new products and new relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to maintain and develop new relationships with third-party foundries, adoption of technologies by semiconductor companies and increases in the demand for their products, the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies, the company's ability to obtain royalty revenues from customers in addition to license fees, business and economic conditions generally and in the semiconductor industry in particular, competition in the market for embedded memories and other risks including those described in the Company's Annual Report on Form 10-K for the period ended September 30, 2002, filed with the Securities and Exchange Commission (SEC) on December 16, 2002, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic or from the SEC's website (www.sec.gov), and in press releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.
All trademarks and copyrights are property of their respective owners and are protected therein.
|
Related News
- ARC Extends Reach in Medical Device Market On New License Agreement with Boston Scientific
- Virage Logic targets China with SMIC IP license agreement
- Virage Logic Announces License Agreement with STMicroelectronics for Embedded Memory IP in 90NM
- Tower Semiconductor and Virage Logic Announce License Agreement of NOVeA Family of Embedded Non-Volatile Memories
- Google extends license agreement for AAC codec range with Fraunhofer IIS
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
E-mail This Article | Printer-Friendly Page |