Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
TransEDA Launches New Rule-Sets In ``Ready-To-Use'' HDL Checking Software
TransEDA Launches New Rule-Sets In ``Ready-To-Use'' HDL Checking Software
LOS GATOS, Calif.--(BUSINESS WIRE)--June 18, 2001-- TransEDA, the leader in ready-to-use verification solutions, today launched VN-Check 2.1, a configurable HDL checker with new rule-sets that will improve productivity as design engineers catch more bugs earlier in the design process.
With VN-Check, users can organize checks into rule-sets, allowing fast, targeted analysis of specific design characteristics such as finite state machines, design for test or design for reuse. Rule-sets can easily be created and shared among team members for improved productivity. VN-Check now comes standard with rule-sets for design for test (DFT), finite state machine (FSM), field programmable gate array (FPGA), synthesis, OpenMore, Reuse Methodology Manual (RMM) Best Practices and Verilog-VHDL portability.
``These new rule-sets allow VN-Check to be used out of the box for a wider variety of analyses,'' said Tom Borgstrom, vice president of marketing at TransEDA. ``Our goal is to make it easier for our customers to focus on capturing their design while relying on VN-Check to analyze the design and catch serious bugs in their code before moving on to simulation.''
The new version also includes automatic FSM extraction, analysis and display, complementing the static checks in the new FSM rule-set.
``Finite state machines are used for critical control logic in many designs,'' Borgstrom said. ``They deserve special attention during pre-simulation verification.''
Along with VN-Check 2.1, TransEDA is also offering an optional package, VN-Check CRC, a custom rule-creation package that enables power users and corporate CAD groups to create their own rules that can be used with VN-Check. These rules now can be defined using Perl with a sophisticated application programming interface (API) and a graphical rule development interface to quickly create a rule template and compile the rule for use in VN-Check.
``Designers and CAD managers are familiar and comfortable with Perl, so we wanted to make this interface available so they could create their own rules more easily,'' Borgstrom said.
Verification Navigator
VN-Check 2.1 Configurable HDL Checker is part of TransEDA's Verification Navigator integrated design verification environment. Verification Navigator provides a suite of tools that enable IC designers to manage the verification process and shorten verification time. In addition to VN-Check, Verification Navigator includes VN-Cover(TM) Coverage Analysis, VN-Control(TM) Application Specific Test Automation and VN-Optimize(TM) Test Suite Analysis.
Verification Navigator supports all leading Verilog, VHDL and dual-language simulation environments including Cadence Affirma NC-Verilog, NC-VHDL, NC-Sim, Verilog-XL and Leapfrog; Model Technology ModelSim Verilog, ModelSim VHDL and ModelSim SE; and Synopsys VCS, Scirocco and VSS. Verification Navigator is available on Solaris, HPUX, AIX, Linux, Windows NT and Windows 2000 platforms.
Pricing and Availability
VN-Check 2.1 is priced from $20,000 U.S. and is available immediately. VN-Check CRC is priced from $15,000 U.S. for a one-year subscription, and is available immediately.
About TransEDA
TransEDA PLC (symbol TRA on the London Stock Exchange) develops and markets ready-to-use verification solutions for electronic field programmable gate array (FPGA), application-specific integrated circuit (ASIC) and system on a chip (SoC) designs. The company's verification IP library includes models for advanced microprocessors and bus interfaces. The company's design verification software performs application specific test automation, configurable HDL checking, functional, FSM and code coverage analysis and test suite analysis. TransEDA's tier-1 list of customers includes 18 of the top 20 semiconductor vendors. For more information, contact TransEDA at 985 University Avenue, Los Gatos, Calif. 95032, telephone 408/335-1300, fax 408/335-1319, email info@transeda.com, or visit http://www.transeda.com.
Contact:
TransEDA, Los Gatos
Tom Borgstrom, 408/335-1303
tom.borgstrom@transeda.com
or
Cayenne Communication
Michelle Clancy, 252/940-0981
michelle.clancy@cayennecom.com
or
PentaCom
Sharon Graves, +44 1242 525205
sharon.graves@btinternet.com
Related News
- HDL Design House selects Silicon Frontline's P2P Software for Fast, Easy IR Drop and Resistance Mapping
- Aldec sets a new paradigm with a single platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC designs
- New Mentor Embedded ReadyStart Provides Highly Integrated, Ready-to-Use Software Platform for Embedded Systems Development
- ATEME launches EASEE: Audio/Video Software System for TI's DaVinci Technology
- ATEME launches EASEE: Audio/Video Software System for TI's DaVinci Technology
Breaking News
- Kudelski IoT and PUFsecurity Combine IoT Security Strengths to Meet the Challenges of Increasing Global Regulation
- Alphawave Semi Joins UALink™ Consortium to Accelerate High-Speed AI Connections
- AST SpaceMobile and Cadence Collaborate to Advance the World's First and Only Planned Space-Based Global Cellular Broadband Network
- Intel CEO's Departure Leaves Top U.S. Chipmaker Adrift
- Post-Quantum Cryptography: Moving Forward
Most Popular
- Intel Announces Retirement of CEO Pat Gelsinger
- Tenstorrent closes $693M+ of Series D funding led by Samsung Securities and AFW Partners
- Lip-Bu Tan quit Intel board after "differences" with CEO, says Reuters
- MIPS Releases P8700, Industry's First High-Performance AI-Enabled RISC-V Automotive CPU for ADAS and Autonomous Vehicles
- Arteris Deployed by Menta for Edge AI Chiplet Platform
E-mail This Article | Printer-Friendly Page |