0-In Design Automation to Present at Verisity's Worldwide Next-Generation Verification Seminar Series

Seminars will teach engineers how to achieve verification closure in complex chip development projects

SAN JOSE, Calif. - September 3, 2003 - Today 0-In Design Automation, the Assertion-Based Verification Company, announced that the company will be presenting at Verisity, Ltd.'s (Nasdaq:VRST) worldwide Autumn seminar series on verification methodology. The Next-Generation Verification Seminars will introduce Verification Process Automation (VPA) solutions and offer a step-by-step look at what it takes to achieve first-pass silicon success with today's extremely complex chips, systems, hardware and software systems and systems-on-chip. In addition, attendees will get a sneak peek at innovative new verification automation technologies that enable verification closure.

The seminars are highly technical, focusing on VPA methodologies and techniques. Verisity will discuss concepts in driving verification closure by using verification metrics and process automation and show how these techniques scale from the module to the chip and the system level. 0-In will discuss structural coverage, a set of unified coverage metrics that link simulation with formal verification to provide users with actionable feedback about functional verification progress. These metrics support effective use of assertion-based verification, reduce total verification effort, and allow for earlier tape out with greater confidence.

At the seminars, attendees will learn:

Strategies that deliver results, beginning with verification plan creation
Total coverage as the metric for verification closure
Use of static, simulation, and formal structural coverage for best results
How an assertion methodology fits into an overall testbench strategy
Automation of the verification process
Verification reuse strategies that improve efficiency and deliver results.

Seminar Schedule and Registration
The Next-Generation Verification seminar series will be offered worldwide; 0-In will participate in all the seminars in North America, Japan and Korea as follows:

September 15: Los Angeles, CA
September 16: Irvine, CA
September 17: San Diego, CA
September 23: Santa Clara, CA
October 7: Ottawa, ON
October 9: Waltham, MA
October 14: Denver (Broomfield), CO
October 21: Dallas, TX
October 23: Austin, TX
October 31: Kyoto, Japan
November 5: Tokyo, Japan
November 7: Seoul, Korea

Attendance at the seminars is free. Registration information and more details on the seminar contents are available at http://www.verisity.com/home/seminar2003/index.html or by sending an email to seminars@verisity.com or seminars@0-In.com.

About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.

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0-In® and CheckerWare® are registered trademarks of 0-In Design Automation, Inc.