Lexra fields NetVortex trial chip

Lexra fields NetVortex trial chip
By Peter Clarke, EE Times
June 11, 2001 (1:01 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010611S0013

LONDON — Lexra Inc. (San Jose, Calif.) is due to present details of its NetVortex architecture and the specifics of its implementation in the NetVortex PowerPlant processor at the Embedded Processor Forum this week.

Lexra will describe NetVortex as part of a new themed day at this year's Embedded Processor Forum called the Network Processor Forum.

Lexra's NetVortex PowerPlant processor integrates sixteen LX8380 32-bit RISC processors on a chip that operates at up to a 420-MHz clock frequency, and features a two-stage crossbar switch that connects to a selection of dedicated metering, analysis and statistics memory resources. Major memory resources are off-chip .

Each processor runs an instruction set based on the original MIPS-I instruction set, but extended by Lexra to provide specific support for many functions required of routers and protocol engines.

Lexra's business model to date has been based on licensing processor intelle ctual property. "This is our first product," said Charlie Cheng, president and chief executive officer of Lexra. "It is a chip version of the NetVortex architecture, but it is intended for licensees only. It's a field trial chip for customers to get to market quickly."

Like many other companies presenting at the one-day Network Processor Forum, Lexra is targeting the OC-192 and OC-768 transmission standards that call for serial data rates of 10 Gbits/second and 40 Gbits/s respectively. In Lexra's case, the NetVortex PowerPlant (NVP) is described as a general-purpose network processor intended for routing applications at both the core and edge of the network ,as well as inside the data center.

"For Lexra the NVP is a marker of what can be done," said Cheng. "You can add, subtract and scale the architecture. Sixteen processors is fairly optimal, but we could readily extend to 32."

The intention is to allow Lexra licensees to develop prototype systems and let them go to field trials more than one ye ar faster than would be possible with other processors.

Silicon implementation

The NVP has already been implemented in silicon in a 0.13-micron six-metal-layer CMOS process. The chip's 134 square millimeter die consumes 12 watts and is packaged in a 1,157-pin ball-grid array. Delivery of the complete and validated device is scheduled for the fourth quarter.

A block transfer engine connects four SPI-4 64-bit serial buses to the 16 LX8380 processors, which feature a number of innovations to support networking. The most significant is that it allows hardware contexts to be stored and buses to be released while awaiting a result from memory. This allows the NVP to be set up as a multithreaded processor and to have some key memory spaces off-chip without caching data at individual processors and the attendant complex support of cache coherency, said Bob Gelinas, principal architect of the NVP.

Lexra has deliberately chosen to put such features as high-speed SRAM and ternary content add ressable memory off-chip.

The new instructions Lexra has added to the MIPS-I instruction set in the LV8380 are optimized for operations such as bit field manipulation, packet checksum, and support for multithreading.

Multithreading enables the LX8380 to switch context from one packet to another while waiting for slower memory devices such as off-chip CAM and SRAM chips. Each LX8380 has 16 kbytes of instruction memory and 16 kbytes of dual-ported data memory. As a result, the NVP can classify and forward 33 million Layer 3 packets per second.

The NVP also has 128 kbytes of high-speed on-chip SRAM that's shared by the 16 LX8380s. The chip's peripheral devices provide enough data bandwidth for the NVP to perform the necessary table look-ups, context data manipulation, and quality-of-service decisions for OC-192c class routers.

With an available Mips count in excess of 6,000, Lexra intends for the NVP to address the 10-Gbit/s market, but said it plans to get to higher performance from the archi tecture for OC-768c.

"We can get a 40 percent improvement in clock frequency, another 40 percent in instruction set additions and double the number of processors to 32," Gelinas said.

"These are the sort of things our licensees can do behind closed doors," Cheng added.

More Embedded Processor Forum coverage.