Two chip execs cast wary eye on China boom

Robert L. Bailey, the chief executive officer of PMC-Sierra Inc. (Santa Clara, Calif.), foresees a world in which the fabless business model and intellectual-property (IP) outsourcing become mainstream, while China and Asia in general dominate the sales and marketing efforts of companies based in North America and Europe.

Meanwhile, Morris Chang, chairman of silicon foundry giant Taiwan Semiconductor Manufacturing Co., has warned that fab building in China may create a worldwide capacity glut in 2005. "Will there be another recession in 2005? Yes. China will cause it," Chang declared.

Speaking here at the recent Silicon Hills Summit, PMC-Sierra's Bailey predicted that the U.S. trade imbalance with China will grow from $100 billion now to $300 billion in several years. That is raising alarm bells in Washington, he added.

Already, chip sales to Asia are 38 percent of the total, approximately doubling in the last five years, and non-Asian companies are scrambling to understand and compete in Asian markets against local chip suppliers.

While the number of chip design centers in India is mushrooming, Bailey predicted that long-term, China would present the largest opportunity for chip design services because of the high levels of engineering employment there.

Bailey was part of a high-tech CEO squadron that visited Washington in September to meet with congressional leaders. "I can tell you that corporations are not very popular in Washington these day, not among the Democrats and not among many of the Republican congressmen we spoke to, either," he said. Corporate governance, and higher standards of personal honesty, are needed if companies are to maintain credibility and fend off assaults on corporate tools such as stock options, he said .

Bailey said mask costs, rising to $1 million for a 90-nm mask set and $1.7 million for a 65-nm mast set, will bring changes. Startups will have a harder time getting on their feet. Also, the number of ASIC starts will continue to see pressure, while FPGAs, structured arrays and microprogrammable solutions will become the de facto ASICs of the future, he said.

Nevertheless, Bailey said he expects to see an "explosion" of system-on-chip designs in coming years, partly fueled by progress in commercial IP. As the chip business continues to de-integrate, relying on foundries, IP providers and other independent vendors, the industry must be on guard against "margin stacking" that would bloat chip costs, he warned.

Semiconductor companies in general are moving away from sales representatives to direct sales, a change from the first few decades of the chip industry. And companies are emphasizing profitability, rather than sheer growth; price/performance rather than raw performance; and prog rammability rather than fixed or hardwired solutions, said Bailey.

Feast or famine?

TSMC's Chang spoke about China at the recent Taiwan+China Semiconductor Outlook Conference in San Jose, Calif. While Bailey worries about a "severe" wafer shortage in 2004 or 2005 (see Oct. 6, page 96), Chang sees the opposite.

China is building fab capacity at an alarming rate, he said, causing Chang and others to believe that the IC market faces another cyclical round of semiconductor overcapacity by 2005. By then, China's chip makers, small fry at the moment, will have an impact in the overall IC supply/demand situation, he said.

Discussing a "post-Moore's Law" era, Chang said that costs are simply too steep to maintain the breakneck, two-year cycle of Moore's Law. "We can't afford these expensive designs anymore. It takes $30 million just to get a design out," he said. "Economically, Moore's Law will have to slow down."