Verification steps forward with DAC launches

Verification steps forward with DAC launches
By Richard Goering, EE Times
June 11, 2001 (4:39 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010611S0118

LAS VEGAS — Functional verification technology will take a step forward at next week's Design Automation Conference (DAC) as several EDA vendors roll out offerings. Axis Systems and Forte Design Systems are claiming technology breakthroughs with new products, while Co-Design Automation, TransEDA, Tharas and Cadence Design Systems are adding to existing offerings.

Axis will launch Xpert, a new family of hardware/software co-verification systems based on the company's reconfigurable computing (RCC) hardware engine. The company will hold a press conference Monday, June 18, to provide details about the first family member, which will offer co-verification for ARM cores.

Axis' RCC engine underlies both its Xcite simulation accelerators and Xtreme emulators. Xpert is additional software that works with either product. Axis intends to launch separate Xpert products for different processor models. Steve Wang, v ice president of marketing, said that after ARM, Axis will target embedded processors from ARC, Lexra, MIPS and IBM.

Axis claims its new product is distinct from existing hardware/software co-verification systems in several ways. For one, the company claims that RCC's acceleration is up to three orders of magnitude faster than software simulators. Unlike emulation providers, Wang said, Axis offers event-driven verification, which means that the whole simulation stops when a software breakpoint is encountered.

Wang also said that Xpert handles hardware and software verification as a "single process," and does not use an external processor model. Xpert employs register-transfer-level processor models, which promise much greater accuracy than instruction-set models. But users must buy these models separately from the processor vendors.

An "instant trace" capability lets users save history data, and go back in time to view any point in software execution. While instant trace is a postprocessing capab ility, Xpert's "instant resume" feature works in real-time. It lets users restart simulation at a given point and advance from there, running live simulation.

Xpert users continue to work with their existing software debuggers. The idea, Wang said, is that the co-verification "runs and feels just the same" as if software developers were running code on the completed silicon. But Xpert is still well below real-time speeds; it will typically run around 500 kHz, Wang said. Axis will release pricing and configuration details for the ARM-based Xpert system at DAC.

Forte's Perspective

Forte, the new EDA company formed from the merger of Chronology and CynApps, will roll out Perspective, a results analysis tool. Forte claims Perspective, which works in run-time or postprocessing environments, is the first "language-independent" verification results analysis tool.

"With Perspective, we've separated data generation from data analysis," said Jacob Jacobs son, Forte's president and chief executive officer. "Typically designers mix them inside of testbenches. But by separating them, we can speed simulation and, more important, collect a database of results that you can go through and analyze."

Forte provides a temporal analysis, which probes relationships between signals and transactions. It offers pattern matching, which permits users to see if a stream of data matches a given pattern. It also has a "visualization and exploration" graphical user interface that lets users view transactions as waveforms, thus working at a high level of abstraction. Finally, it includes a functional coverage check.

Perspective is a plug-in product for Forte's recently announced GigaScale Hub, but it does not require the entire QuickBench product. Its specification language is a subset of Forte's Rave language, with C+ to follow shortly, but Perspective can work with Verilog, VHDL, C++ or Rave testbenches. Perspective is available now for $20,000. The GigaScale Hub starts at $5,000.

Adds to Superlog

Another way to speed testbench development, according to Co-Design Automation, is by using that company's Superlog language. Co-Design has added features to Superlog for automating testbench generation, and has made changes to its Systemsim simulator to speed verification. New capabilities within Systemsim include random test generation, functional test coverage, assertion and property checks, plus data manipulation and queueing functions.

A new simulation algorithm, called Universal for Unified Verification Simulation Algorithm, allows verification functions to be carried out directly from the simulation kernel. The claimed benefit is the elimination of interpreted external test-generation mechanisms that have to be indirectly coupled to simulation engines through the programming language interface (PLI).

Co-Design claims that the scheduling of events within a single kernel can produce a fourfold speed improvemen t over PLI-based environments. In addition, simulation debug utilities operate on both the design and testbench at the same time.

The name given to the expanded simulation kernel within Systemsim is Supercharger. Co-Design said it has embedded several functional test automation capabilities to detect "corner cases" and reduce testbench-coding effort and simulation cycles. It still supports the C-blend facility that allows Verilog and Superlog descriptions to be called from a C/C++ program.

For its part, TransEDA plans to debut a library of system-level verification models at DAC based on models acquired with iMODL Inc. (San Jose, Calif.) in March. IMODL was known for its Intel processor models and the library has now been integrated with TransEDA's Verification Navigator software tool.

The library offers processor bus-functional models, standard bus agents and monitors, and functional coverage models for use in Verification Navigator or with third-party HDL verification environments. TransEDA has relabeled them Foundation Models and is making them available starting at $10,000 to $20,000 for a one-year subscription license. TransEDA will also introduce a new product, VN-Control, an application-specific test automation tool for HDL designs. Featuring automatic test generation and results checking from a test template — no new languages are needed — it can be used with Foundation Models and HDL simulators to provide a test environment for target applications. VN-Control is priced at $5,000 to $30,000 (one-year subscription license).

Tharas Systems, meanwhile, is releasing 2 million- and 4 million-gate versions of its Hammer 50/32 simulation accelerator, until now available only in an 8 million-gate configuration. Users who don't need that capacity get a "dramatic" price/ performance improvement with one of the lower-capacity products, said Prabhu Goel, Tharas chairman and chief executive officer.

The Hammer 5 0/32-2M is priced at $115,000 and the Hammer 50/32-4M at $185,000, against $280,000 for the 8 million-gate Hammer 50/32-8M. All use the same hardware and offer the same performance and functionality.

Verification models

Finally, Cadence Design Systems will roll out reusable transaction verification modules (TVMs) for use with that company's new Verification Cockpit 2.0 release, as well as the TestBuilder open-source C++ class library. Initial TVMs include transaction-based models for the ARM AHB and APB buses, Utopia levels 1, 2 and 2Tx/Rx, and a compliance checker for the Infiniband link layer. If purchased off the shelf, the TVMs are typically priced from $15,000 to $25,000. They can also be part of a services engagement through Cadence's Verification Reuse Methodology program.

Peter Clarke contributed to this story.