English
Cypress Speeds CPLD Programming with In-System Reprogrammable Software
ISR™ Release 4.0 and Development Kit Support SVF and Chain-Independent STAPL Files For Embedded Programming Applications
SAN JOSE, Calif., November 24, 2003 - Cypress Semiconductor Corporation (NYSE: CY) today announced availability of Release 4.0 of its In-System Reprogrammable (ISRTM) software for CPLDs. ISR refers to the ability to reprogram Cypress CPLDs even when they are mounted on a circuit board. Cypress also announced its latest development kit (CY3950I), featuring a USB 2.0 / 1.1 programming cable, which enables up to ten times improvement in programming speed over previous versions of the ISR software. These recent additions, combined with Cypress’s WarpTM Release 6.3 software, round out the company’s full arsenal of tools to support its Ultra37000™ and Delta39K™ CPLD families.
In addition to supporting the world’s largest CPLDs, ISR Release 4.0 adds a new layer of capabilities and compatibility by supporting the Serial Vector Format (SVF). SVF is a widely-adopted industry standard used to describe Joint Test Action Group (JTAG) signals in a more compact way than Standard Test and Programming Language (STAPL), making it more suitable in certain embedded programming applications.
ISR Release 4.0 also extends its JEDEC STAPL support by adding the ability to create Chain Independent (CI) STAPL files. The ability to create CI STAPL files, in addition to the STAPL Chain Dependent files supported by previous versions of ISR, provides further compatibility with third-party JTAG tools. New features present in ISR Release 4.0 include improved chain validation functionality as well as a new Checksum Operation, designed to guarantee programming file integrity. ISR Release 4.0 supports Windows XP, Windows 2000, Windows ME, Windows 98 SE, Windows NT 4.0 Service Pack 5 or later.
“Cypress has long history of providing designers with the best tool set possible,” said Gahan Richardson, senior marketing manager of Data Communications products for Cypress Semiconductor. “With this major increase in performance for our CPLD tools, we’ve significantly reduced design time, resulting in faster time-to-market for our customers.”
ISR Release 4.0 reduces design time in several ways. The latest release eliminates the need to recompose the STAPL file before executing a new STAPL operation. A more user-friendly GUI detects all devices connected in the JTAG chain and automatically populates the GUI with these devices. Additionally, ISR Release 4.0 supports a new Playlist feature that allows multiple operations to be specified in a Playlist; these operations can then be executed consecutively on a single or multiple devices in the JTAG chain.
Pricing and Availability
As with earlier versions of ISR, Release 4.0 may be downloaded free from the Cypress Website at http://www.cypress.com/support/link.cfm?sd=isr4 . The development kit (CY3950I) is available now from Cypress’s online store (http://www.onfulfillment.com/cypressstore/) for $99.
About Cypress
Cypress Semiconductor Corporation (NYSE: CY) is Connecting From Last Mile to First Mile™ with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress Connects™ using wireless, wireline, digital, and optical transmission standards, including USB, Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and reconfigurable mixed-signal arrays. More information about Cypress is accessible online at www.cypress.com.
# # #
Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. ISR, Warp, Delta39K, Ultra37000, “Connecting From Last Mile to First Mile” and “Cypress Connects” are trademarks of Cypress. All other trademarks are the property of their respective owners.
SAN JOSE, Calif., November 24, 2003 - Cypress Semiconductor Corporation (NYSE: CY) today announced availability of Release 4.0 of its In-System Reprogrammable (ISRTM) software for CPLDs. ISR refers to the ability to reprogram Cypress CPLDs even when they are mounted on a circuit board. Cypress also announced its latest development kit (CY3950I), featuring a USB 2.0 / 1.1 programming cable, which enables up to ten times improvement in programming speed over previous versions of the ISR software. These recent additions, combined with Cypress’s WarpTM Release 6.3 software, round out the company’s full arsenal of tools to support its Ultra37000™ and Delta39K™ CPLD families.
In addition to supporting the world’s largest CPLDs, ISR Release 4.0 adds a new layer of capabilities and compatibility by supporting the Serial Vector Format (SVF). SVF is a widely-adopted industry standard used to describe Joint Test Action Group (JTAG) signals in a more compact way than Standard Test and Programming Language (STAPL), making it more suitable in certain embedded programming applications.
ISR Release 4.0 also extends its JEDEC STAPL support by adding the ability to create Chain Independent (CI) STAPL files. The ability to create CI STAPL files, in addition to the STAPL Chain Dependent files supported by previous versions of ISR, provides further compatibility with third-party JTAG tools. New features present in ISR Release 4.0 include improved chain validation functionality as well as a new Checksum Operation, designed to guarantee programming file integrity. ISR Release 4.0 supports Windows XP, Windows 2000, Windows ME, Windows 98 SE, Windows NT 4.0 Service Pack 5 or later.
“Cypress has long history of providing designers with the best tool set possible,” said Gahan Richardson, senior marketing manager of Data Communications products for Cypress Semiconductor. “With this major increase in performance for our CPLD tools, we’ve significantly reduced design time, resulting in faster time-to-market for our customers.”
ISR Release 4.0 reduces design time in several ways. The latest release eliminates the need to recompose the STAPL file before executing a new STAPL operation. A more user-friendly GUI detects all devices connected in the JTAG chain and automatically populates the GUI with these devices. Additionally, ISR Release 4.0 supports a new Playlist feature that allows multiple operations to be specified in a Playlist; these operations can then be executed consecutively on a single or multiple devices in the JTAG chain.
Pricing and Availability
As with earlier versions of ISR, Release 4.0 may be downloaded free from the Cypress Website at http://www.cypress.com/support/link.cfm?sd=isr4 . The development kit (CY3950I) is available now from Cypress’s online store (http://www.onfulfillment.com/cypressstore/) for $99.
About Cypress
Cypress Semiconductor Corporation (NYSE: CY) is Connecting From Last Mile to First Mile™ with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress Connects™ using wireless, wireline, digital, and optical transmission standards, including USB, Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and reconfigurable mixed-signal arrays. More information about Cypress is accessible online at www.cypress.com.
# # #
Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. ISR, Warp, Delta39K, Ultra37000, “Connecting From Last Mile to First Mile” and “Cypress Connects” are trademarks of Cypress. All other trademarks are the property of their respective owners.
|
||||||
Related News
- Siemens' Tessent In-System Test software enables advanced, deterministic testing throughout the silicon lifecycle
- 8051 MCUs get In-System Programming Benefits Through CAST and SMH Technologies Partnership
- Coherent Logix And Intrinsic-ID Announce Availability Of An Advanced Secure Processor Enabling Fully Software Reprogrammable Wireless and Video Solutions for Software Defined Systems
- New Actel Low-Cost Starter Kit Demonstrates Secure In-System Programmability of ProASIC3/E FPGAs
- Green Hills Software's INTEGRITY RTOS Speeds Complex System Deployment with Integration of Texas Instruments DSP/BIOS Link
Breaking News
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |