English
TriCN introduces RLDRAM II Interface IP
New High-Performance Memory Interface Addresses Growing Bandwidth Demand in Communications and Storage Markets
SAN FRANCISCO, CA – December 15, 2003-- TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology today announced the immediate availability of its Reduced Latency (RL) DRAM II interface, the latest member of its Interface Specific I/O (ISI/O) product family. Based on High Speed Transistor Logic (HSTL)-18 I/O pads targeted for RLDRAM II applications, the interface is capable of up to 800 Mb/s operation, and is backward compatible with the original RLDRAM interface.
“RLDRAM II is a powerful interface that not only serves the ever-increasing performance demands in the networking and communications market, but also offers designers an alternative to QDR SRAM,” says Ron Nikel, CTO for TriCN. “At 800 Mb/s performance, the RLDRAM II interface is a product that can immediately satisfy the very high-end of bandwidth demand in the memory interface market.”
RLDRAM II technology offers low random Read/Write Cycle Times similar to that of SRAMs, making it an attractive choice for high bandwidth communications and storage applications, including Switches, Routers, and Server caches. TriCN’s RLDRAM II interface is optimized for high-speed operation with a double data rate I/O for increased bandwidth, and offers dedicated I/O structures for Data, Clock and Address.
Availability
TriCN's RLDRAM II interface is immediately available in the TSMC 0.13um process.
ISI/O: Interface Specific I/O Solutions
TriCN has created a family of validated and complete ISI/Os that are tailored to specific interface applications. Based on generic, broadly applicable interface standards (such as HSTL, SSTL, LVDS), these products have been developed to account for the complete range of environmental constraints at the chip and system level. This enables seamless integration into chip development, and allows customers to achieve high performance targets, while reducing time-to-market. Moreover, this pre-validation of the design significantly reduces risk for IC developers. In particular, TriCN’s ISI/Os are targeted toward communications, memory and graphics applications, and include products such as DDRII-SDRAM, GDDRII, QDR-SRAM, DDR-FCRAM II, SPI-4.2, and HyperTransport.
About TriCN
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip, ranging from a Base I/O library to multi-gigabit SerDes products. This IP is designed for IC developers addressing bandwidth-intensive applications in the communications, networking, data storage, and memory space. TriCN's customers range from startup to established fabless semiconductor and systems companies, including Philips, General Dynamics, SGI, IBM, Cognigine, Internet Machines, and Apple Computer.
For more information, please visit TriCN’s web site at www.tricn.com.
TriCN: High Performance Interface Specialists
SAN FRANCISCO, CA – December 15, 2003-- TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology today announced the immediate availability of its Reduced Latency (RL) DRAM II interface, the latest member of its Interface Specific I/O (ISI/O) product family. Based on High Speed Transistor Logic (HSTL)-18 I/O pads targeted for RLDRAM II applications, the interface is capable of up to 800 Mb/s operation, and is backward compatible with the original RLDRAM interface.
“RLDRAM II is a powerful interface that not only serves the ever-increasing performance demands in the networking and communications market, but also offers designers an alternative to QDR SRAM,” says Ron Nikel, CTO for TriCN. “At 800 Mb/s performance, the RLDRAM II interface is a product that can immediately satisfy the very high-end of bandwidth demand in the memory interface market.”
RLDRAM II technology offers low random Read/Write Cycle Times similar to that of SRAMs, making it an attractive choice for high bandwidth communications and storage applications, including Switches, Routers, and Server caches. TriCN’s RLDRAM II interface is optimized for high-speed operation with a double data rate I/O for increased bandwidth, and offers dedicated I/O structures for Data, Clock and Address.
Availability
TriCN's RLDRAM II interface is immediately available in the TSMC 0.13um process.
ISI/O: Interface Specific I/O Solutions
TriCN has created a family of validated and complete ISI/Os that are tailored to specific interface applications. Based on generic, broadly applicable interface standards (such as HSTL, SSTL, LVDS), these products have been developed to account for the complete range of environmental constraints at the chip and system level. This enables seamless integration into chip development, and allows customers to achieve high performance targets, while reducing time-to-market. Moreover, this pre-validation of the design significantly reduces risk for IC developers. In particular, TriCN’s ISI/Os are targeted toward communications, memory and graphics applications, and include products such as DDRII-SDRAM, GDDRII, QDR-SRAM, DDR-FCRAM II, SPI-4.2, and HyperTransport.
About TriCN
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip, ranging from a Base I/O library to multi-gigabit SerDes products. This IP is designed for IC developers addressing bandwidth-intensive applications in the communications, networking, data storage, and memory space. TriCN's customers range from startup to established fabless semiconductor and systems companies, including Philips, General Dynamics, SGI, IBM, Cognigine, Internet Machines, and Apple Computer.
For more information, please visit TriCN’s web site at www.tricn.com.
TriCN: High Performance Interface Specialists
|
||||||
Related News
Breaking News
- Arm loses out in Qualcomm court case, wants a re-trial
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
Most Popular
|
E-mail This Article | 
|
|
Printer-Friendly Page |