Aptix Introduces Pathfinder IP Validation Station

Low cost unit incorporates Altera Stratix FPGA

SAN JOSE, Calif. – December 15, 2003 -- Aptix Corporation, a leading supplier of pre-silicon prototyping tools and platforms for embedded system-on-chip (SoC) design, today announced the immediate availability of its Pathfinder™ IP Validation Station built incorporating a single Altera Stratix FPGA and utilizing Aptix Expeditor™ Co-emulation technology. Users can choose either a Stratix EP1S30 or EP1S80 configuration.

“Many of our customers have requested support for Altera technology,” said Charlie Miller, Sr. VP of Marketing and Business Development at Aptix. “Pathfinder is perfect for design teams that are targeting a final implementation in a Stratix device or want to validate IP blocks running at very high speed. Pathfinder is a joint development with Galaxy Far East Corp., our distributor in Taiwan. Their experience as Altera’s distributor in Taiwan was invaluable in bringing this product to market.”

The Aptix Pathfinder IP Validation Station provides a prototyping platform for small, embedded SoC designs or for embedded IP blocks, incorporates an Altera Stratix™ EP1S30 or EP1S80 FPGA, and provides a capacity of up to 470,000 ASIC logic gates and up to 7.4 million bits of embedded RAM. Because of its compact size--9.5"x 11.5"x 2.75"-- and easy connection to a local workstation, the Pathfinder IP Validation Station is the perfect platform for IP validation and early software development.

The Pathfinder IP Validation Station comes configured with Aptix Expeditor co-emulation. Using this capability, designers can use their simulation testbenches to provide stimulus and check response for designs loaded on the Pathfinder IP Validation Station. The speed of the Pathfinder IP Validation Station cuts regression test times by orders of magnitude compared with software simulators. This makes the Pathfinder IP Validation Station especially useful for validating communication protocol compliance of blocks of an embedded SoC design. Support for transaction-level testbenches provides another order of magnitude improvement in performance.
The Pathfinder IP Validation Station is usable throughout the development cycle from project start to silicon. A key advantage of the Aptix solution is that much software development work can be done before tape-out or after tape-out while developers are waiting for silicon.
The Pathfinder IP Validation Station includes powerful debugging capabilities through the included Aptix Expeditor Co-emulation interface. Aptix Expeditor allows users to drive the DUT with testbenches developed for a software simulator, and monitor signals in the DUT for debugging purposes.

Price, Availability
The Pathfinder IP Validation Station is priced at $30,000, including the Aptix Expeditor Co-Emulation interface. It is available for immediate shipment.

About Aptix
Aptix Corporation provides tools for modeling SoC designs using multiple FPGA devices and silicon intellectual property. These models are used for system hardware creation and integration, as system hardware verification platforms, as prototypes for firmware and application software development, as validation platforms for software integration and real-world system testing and as pre-silicon prototypes for early customer product evaluation.

Notes to editors:
A Pathfinder IP Validation Station data sheet, picture and flow diagram are available on request.
Expediter was formally called MVP. More information is at http://www.aptix.com/products/expeditor.htm

Aptix® and the Aptix logo are registered trademarks of Aptix Corporation. Pathfinder IP Validation Station and Expeditor are trademarks of Aptix Corporation.
All other registered trademarks or trademarks are property of their respective owners.

Aptix is located at 1249 Innsbruck Drive, Sunnyvale, CA 94089, USA.

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