90-nm complexity may not raise per-die costs

90-nm complexity may not raise per-die costs
By Loring Wirbel, EE Times
February 10, 2004 (11:11 a.m. EST)
URL: http://www.eetimes.com/story/OEG20040210S0015

MONTEREY, Calif. — The greater area of 300-mm wafers may make up for the cost of process complexity and 90-nm feature sizes and below, Edward So of Intel Corp. said during a Globalpress Summit panel on process technologies Monday (Feb. 9).

So, vice president and director of Intel's California technology and manufacturing center, said analysts often focus on the absolute cost of building new fabs without realizing that “wafer area compensates for process complexity.”

The status of 90-, 65- and 45-nm CMOS processes was a key topic in the panel chaired by EE Times Editor-in-Chief Brian Fuller. Panelists refused to speculate on which companies had taken 90-nm CMOS production to 5,000 or 10,000 wafer starts per month.

However, Julie England, vice president and business manager at Texas Instruments Inc., did say the production ramp was so steep for most companies that the difference between the two numbers over a few months' time was a lmost negligible. She added that TI's 90-nm wafer starts ranged from 1,000 to 5,000 per month, and that two UltraSparcs, one DSP processor and one digital baseband processor had sampled at that feature size.

Many companies have 65-nm processes in preproduction, and 45-nm work is not far behind. Gregg Higashi, chief technology officer for front-end tools at Applied Materials Inc., said major semiconductor players have already invested in 45-nm basic research.

Intel's So said it has begun basic development work, TI's England said most larger IC manufacturers were working on “unit process flow for individual gate research at 45 nm.”

Panelists dismissed questions about "disruptive" processes, predicting instrad a continued life for bulk CMOS despite increasing costs for lithography below 90 nm. England said “those of us who have been in this field for decades never thought bulk CMOS would last this long.”

Keynote speaker Tsugio Makimoto, Sony Corp.'s senior corporate advisor, argued that consumer robotics constitute a “fourth wave” of innovation to drive IC design, following analog, PC wave and mobility and networking waves of the past. Makimoto said integration of sensors and actuators in design would cause a tangential wave of “cleverness-driven devices” to augment Moore's Law.

He cited Sony's Network Walkman, and its “Virtual Mobile Engine,” as proof that system-on-chip concepts still bear relevance in consumer electronics. While SoC has been hyped, with many resulting design lags, the single-chip methodology must be complemented with silicon-in-package technology utilizing advanced hybrid concepts, Makimoto said.