English
Chipidea announces silicon validated analog IP cores in Chartered 0.18um CMOS Process
Update: MIPS Technologies Acquires Chipidea (August 27, 2007)
Porto Salvo, Portugal – February 23 2004, ChipIdea Microelectrónica, S.A., a leadinganalog and mixed-signal IP and SOC provider, has successfully validated in
Chartered 0.18um CMOS process a complete set of analog/mixed-signal IPs Cores
designed to cover a wide range of Analog Front-End requirements for wireless,
wireline and multi-media applications.
These IP Cores include:
- CI8225aa-10bit, 14MHz Current-Steering DAC
- CI8232aa-10bit 500kHz DAC
- CI7226aa- Audio 16 bit sigma-delta codec
- CI3227aa-8bit, 14MHz pipeline ADC
- CI3231aa-10bit, 100kHz SAR ADC
- CI2228aa-Power on reset with references
- CI2230aa-Distributed Voltage Regulator
- CI1229aa-240MHz clock multiplying PLL
- CI12233aa-USB2.0 LS/FS AFE
To see the whole report, please visit
http://www.chipidea.com/website_45c/ciflash/2004_2/flashnews19022004.html
|
||||||
Related News
- ChipIdea's 210MHz Analog Interface for Flat Panel Displays Validated in Silicon at 0.18um TSMC
- Atmel Announces 0.18um RF CMOS Foundry Process for Low Volume Applications
- Faraday Announces Ultra-High-Density miniIP Silicon IP Platform for UMC 0.18um Process
- SMIC Adds New Design Kit for its 0.18um CMOS Process for Use with Agilent Technologies'EDA Software
- Nordic VLSI launches the nRF2402, a highly integrated component for wireless communication manufactured in an ultra modern 0.18um CMOS process
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
|
E-mail This Article | 
|
|
Printer-Friendly Page |