EDA vendors target memory verification

EDA vendors target memory verification
By Richard Goering, EE Times
May 9, 2001 (7:49 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010509S0063

MOUNTAIN VIEW, Calif. — With this week's introduction of new Spice-like simulators from Synopsys and Celestry Design Technologies Inc., a battle is heating up over memory verification. Until now a relatively small, specialized niche, memory verification is becoming increasingly vital as embedded memory content grows on large systems-on-chip (SoCs).

Memory verification is difficult because it must be done at the transistor level — yet capacities are huge, making traditional Spice simulation impossible. The good news is that memories have regular structures that make hierarchical verification feasible. Vendors are therefore addressing this market with fast, Spice-like simulators with hierarchical capabilities.

The new Synopsys and Celestry simulators target both memory and mixed-signal design. Synopsys' NanoSim represents a combination of that company's TimeMill and PowerMill products, with an added hierarchical capability. Celestry's Ul traSim is a new offering that verifies power, noise, IR drop and reliability, and claims to handle "billion transistor" signoffs.

According to Gary Smith, chief EDA analyst at Gartner Dataquest, these newcomers join a rapidly shifting market. Dataquest includes memory verification as part of the "IC Spice" custom design market. Smith said that MetaSoftware once dominated this market with HSpice, and that Synopsys took it over in 1998 with TimeMill and PowerMill. Then Avanti, which purchased MetaSoftware, reclaimed it in 1999 with Star-Sim, Smith said.

"Today Nassda is giving Avanti a run for the market," Smith said. "Synopsys is trying to regain its position with NanoSim, and Celestry is entering the market with UltraSim. The interesting thing about this market is that the best technology always wins — and fast. Vendors have won or lost this market in a year to 18 months."

Startup InnoLogic Systems offers yet another alternative with it s ESP symbolic simulation product, which maximizes vector throughput by propagating Boolean equations rather than ones and zeroes. Although introduced as a general-purpose tool, ESP today is primarily used for memory verification and for equivalency checking of transistor-level versus behavioral memory models.

NanoSim includes all the capabilities of TimeMill and PowerMill, offering both timing and power verification in one product. It accepts Verilog-A input and boasts a tight interface with Synopsys' VCS Verilog simulator. But for memory designers, NanoSim's most important feature is Synopsys' new hierarchical array reduction (HAR) technology.

"HAR is a significant innovation that takes advantage of the regularity that exists in memories," said Bijan Kiani, vice president of marketing at Synopsys' nanometer analysis and test group. "It uses that knowledge to not duplicate the same verification many times."

Hierarchy is critical, Kiani said, given that a 256-Mbit DRAM can contain more than 586 m illion elements. Synopsys claims NanoSim can verify a 256-Mbit DRAM in "hours." The company won't say how many hours, because it depends on the number of vectors, but Kiani said a typical simulation run will be "a lot less than overnight." Accuracy, he said, is within 3 to 5 percent of Spice.

A key feature of UltraSim for memory designers is its ability to handle both hierarchical and flat netlists at the same time, said Bruce McGaughy, director of R&D at Celestry. In one customer run, he said, a 50-million transistor, 8-bit SRAM simulated in 15 minutes in "fast" mode, which is within 10 percent of Spice accuracy, and in 35 minutes in "accurate" mode, which claims to be within 1 percent of Spice accuracy.

"If you really want a complete post-layout analysis of memory, you're going to have to implement hierarchical extraction," said Dale Pollek, Celestry vice president of marketing. "Put it in the 'coming soon' category from us."

Synopsys and Celestry aren't the first to offer hierarchical Spice-li ke simulators, however. Nassda's HSIM (Hierarchical Simulator) claims to be able to simulate a 256-Mbit DRAM with more than 300 million elements in a few hours on a PC. Avanti, which has greatly sped up Star-Sim with its more recent Star-Sim XT offering, claims to have had hierarchical support since 1997.

Michael Jackson, head of western engineering for Avanti, said that NanoSim and UltraSim are "me-too tools in an established market." Avanti, he said, still leads the pack with HSpice modeling support, foundry sign-off, and accurate parasitic handling.

Simon Napper, InnoLogic chief executive officer, thinks that combining timing, power and functional verification is the wrong approach. Napper argues that functional and timing verification should be separate, and that InnoLogic's functional-only tool provides the best way to maximize vector throughput for complex memories. "We can run the equivalent of ten to the 30th vectors in an hour," he said.

InnoLogic's tool can be used first for transistor- level verification, and later to guarantee the behavioral memory model is identical to the transistor-level model. "We say, use NanoSim or UltraSim for timing and nail that down, and then use us for functionality," Napper said. "We are complementary. We don't do timing."