Altera Introduces Industry’s Fastest and Most Cost-Effective FFT IP Core

New IP Core Is Ideal for FPGA Co-processors Used for Software Defined Radio, Sonar, Image Processing, and Wireless Infrastructure Applications

San Jose, Calif., March 17, 2004—Altera Corporation (NASDAQ:  ALTR) today introduced the industry’s highest performance fast Fourier transfer (FFT) IP core, FFT MegaCore^® Function 2.0, optimized for Altera’s Stratix™ II, Stratix and Cyclone™ FPGA families.  Delivering an unsurpassed combination of high performance, low power, and low cost, this new core will enable system designers to cost-effectively enhance system signal processing by off-loading computationally intensive FFT functions to an FPGA co-processor.

Emerging wireless infrastructure standards, as well as advanced military and air traffic control radar, software defined radio, and military sonar applications, require rapid and highly precise signal processing that strains the capabilities of traditional digital signal processor (DSP) implementations.  FPGA-based co-processors, which are used to off-load computationally intensive functions from digital signal processors, are gaining wide acceptance as an effective means of enhancing overall system performance.  Such co-processors are ideal for implementing the FFT functions critical to many DSP applications.

“Our signal processing applications in air traffic systems require the optimal combination of cost and performance to ensure we deliver the maximum value to our customers,” said Eli Perl, senior system engineer at Sensis Corporation. “After evaluating very high-end FPGA and DSP processor FFT implementations, we chose to use Altera’s new FFT IP core implemented in a Stratix FPGA. The combination of Altera’s FFT IP core and the Stratix FPGA, along with Altera’s good technical support, made it very easy to implement the exact FFT functionality we required, while meeting both our cost and performance requirements.”

Based on a comparison of competitive data, the new FFT core implemented in a Stratix device is five times as fast, costs half as much and has power consumption levels similar to the most advanced DSP FFT implementation in production today.  It is also four times faster than any other FPGA-based FFT core currently available and delivers up to 16K points of resolution.  For example, using approximately 70 percent of a Stratix EP1S20 device’s resources, the FFT 2.0 core delivers a transform calculation time of 1.7µs, while consuming approximately 1.3W of power.  Based on the 10,000 volume unit price of $66 for the EP1S20 device, the effective cost of implementation is $48.

The core delivers a maximum clock frequency in excess of 300 MHz and up to 20 times faster transform calculation times than the previous version of the core, making it ideal for FPGA co-processor implementations. The cost, performance and power benefits can be further enhanced if the design is implemented in a HardCopy Stratix™ structured ASIC device.

Altera’s new fully integrated FFT IP core is comprised of an FFT, data RAM and twiddle ROM and is also optimized to take advantage of the powerful DSP blocks available in the company’s new Stratix II FPGA.  It incorporates a new, easy-to-use IP toolbench graphical user interface and support for Windows, Solaris and Linux operating systems.  The new core features a high throughput quad-output Radix 4 FFT engine that can calculate a 1K-point transform in 1.3 microseconds.  The FFT MegaCore function has support for multiple single-output and quad-output engines in parallel, multiple I/O data flow modes (streaming, buffered burst and burst), an Atlantic™ interface and IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators.

“This new IP core provides a cost-effective path for implementing a co-processor, thereby enhancing the overall system performance,” said Craig Lytle, vice president of Altera’s IP business unit.  “In addition to this new FFT core, Altera has updated our entire portfolio of DSP IP to make it easy for our customers to leverage the industry-leading DSP performance of the new Stratix II device family.”

Pricing and Availability
Altera’s new FFT IP core is available now.  Pricing for a one-time license is $7,999.  For more information about this or other Altera IP cores, please go to www.altera.com/products/ip/dsp/transforms/m-ham-fft.html.

About the Stratix II Device Family
Stratix II FPGAs are the industry’s biggest and fastest FPGAs.  Developed with an innovative new logic structure, Stratix II devices offer over twice the logic density and 50 percent higher performance at 40 percent lower cost than first-generation Stratix devices.  Built on TSMC’s 90-nm, all-copper process, using low-k dielectric material on 300-mm wafers, the new Stratix II logic structure allows designers to conserve device resources by packing more functionality into a smaller area.  For more information about Stratix II devices, please visit www.altera.com/stratix2.

About Altera
Altera Corporation (NASDAQ: ALTR) is the world’s pioneer in system-on-a-programmable-chip (SOPC) solutions.  Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide.  More information is available at www.altera.com.

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Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holder.

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