Lattice Releases IP Core for Serial RapidIO Applications

Intellectual property solution targets high-speed interconnect for chip-to-chip and board-to-board communications

HILLSBORO, OR - March 16, 2004 - Lattice Semiconductor Corporation (NASDAQ: LSCC), the inventor of in-system programmable (ISP^TM) logic products, announced today the immediate availability of an Intellectual Property (IP) core for Serial RapidIO Physical (Phy) Layer interface applications. The new RapidIO Phy core is fully compliant with Revision 1.2 of the RapidIO Interconnect Specification and is targeted at Lattice's ORT82G5 and ORT42G5 Field Programmable System Chips (FPSCs), which combine Lattice's sysHSI^TM SERDES technology with up to 10,000 field programmable gate array (FPGA) logic elements.

"With the introduction of the Serial RapidIO Phy core, we continue to expand our library of IP offerings rapidly," said Stan Kopec, Lattice Semiconductor's vice president of marketing. "Implemented on our popular ORT82G5 and ORT42G5 FPSCs, this RapidIO Phy core demonstrates Lattice's prowess in high-speed interconnect for chip-to-chip and board-to-board communications. As a member of the RapidIO Trade Association, Lattice recognizes the importance of this popular embedded systems architecture, and we've provided a robust, flexible solution for our customers, " Kopec added.

Sam Fuller, president of the RapidIO Trade Association, said: "Lattice Semiconductor's IP solution delivered on a field-programmable SoC (System on Chip) offers the marketplace great value and innovation. Lattice's support of the RapidIO technology is further evidence of the growing acceptance and use of RapidIO in embedded systems. Lattice's SERDES technology and programmable logic expertise provide a flexible and fast time-to-market solution which is essential for success in communications applications like high-speed switching & routing, media gateways, and wireless network controllers."

The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2. The Serial RapidIO Physical Layer is a protocol for packet delivery between Serial RapidIO devices and other devices, including packet transmission, flow control, error management and link maintenance protocols. The core supports one-lane high speed (1x mode) running at 1.0 Gbps, 2.0 Gbps or a maximum of 2.5 Gbps. The IP core includes the following features:

Supports High Speed 1x Mode (up to 2.5 Gbps)
8B/10B Encoding and Decoding
Clock and Data Recovery (CDR)
Lane Synchronization
CRC Generation and Checking
Packet/Control Symbol Assembly and De-assembly
Simple User Interface for Easy Integration into User Logic

Additional information about the Serial RapidIO Phy core is available at the Lattice Semiconductor Web site (http://www.latticesemi.com), including a Data Sheet, User Guide and No-Risk Evaluation Package.

Serial RapidIO Phy IP Core "No-Risk" Evaluation
The Serial RapidIO IP core is part of Lattice's rapidly growing ispLeverCORE^TM library. ispLeverCORE modules are designed using the highest coding standards, and are extensively tested to meet required functionality and performance standards. These cores are ready-to-use, well documented, and are extensively supported by Lattice field and factory engineers.

Lattice provides free "no-risk" evaluations for its Serial RapidIO IP core. The evaluation package can be downloaded at no charge from the Lattice Web site. Customers can use an evaluation model to perform functional simulation of the IP core. The ispLeverCORE evaluation netlist(s) can be instantiated into Verilog and/or VHDL top-level projects. After synthesizing the top-level design (with the core described only as a black box), the entire project is compiled into a Lattice database. Pack, Place, and Route processes can be run to check the fit of the design. Finally, static timing analysis can be run on the evaluation IP using the Performance Analyst^TM tool.

After the ispLeverCORE module is licensed, the customer can continue the implementation and programming flow. The customer is then able to perform full timing simulation, and generate a bitstream file for programming a Lattice device. The Serial RapidIO IP Core is available from Lattice for a one-time price of $15,000.

ORT82G5 and ORT42G5 FPSCs
Lattice's ORT82G5 & ORT42G5 FPSC devices are high-performance programmable devices that combine optimized embedded core functions with flexible, general-purpose FPGA logic. The ORT82G5 and ORT42G5 FPSCs offer 8 and 4 SERDES channels, respectively. In addition to the SERDES channels and over 10,000 ORCA® FPGA logic elements for general-purpose logic, both FPSCs includes fully embedded 8b/10b encoding, XAUI and Fibre Channel link state machines and multi-channel alignment capabilities. The SERDES on the ORT82G5 and ORT42G5 include these best-in-class features:

3.7-0.6Gbps operating range per channel
<225mW per channel worst case at 3.125Gbps
Transmit jitter of 0.17UI at 3.125Gbps
Receive jitter of 0.75UI at 3.125Gbps
Drives 40 inches (1 meter) of FR-4 backplane at 3.125 Gbps
Fast Locking Times with bit realignment in 300 nanoseconds (938 bit times @ 3.125 Gbit/sec)

The ORT82G5 features 372 programmable user I/Os and the ORT42G5 features 204 I/Os supporting a variety of advanced interface standards, including LVCMOS, LVTTL, LVDS, Bus-LVDS, LVPECL, HSTL, SSTL3/2, GTL, GTL+, ZBT and DDR to facilitate easy interfacing.

About the RapidIO Trade Association
The RapidIO Trade Association was formed in June 2000 to drive the adoption of open-standard, high-performance interconnect architectures needed for high-performance networking, communications and embedded systems. With more than 50 member companies worldwide, this non-profit organization is headquartered in Austin, Texas. Membership provides early access to the specifications, the ability to propose changes to the RapidIO standards, and the opportunity to actively participate in the adoption process. A complete list of member companies, as well as education and design tools, are available at the association's website http://www.RapidIO.org.

About Lattice Semiconductor
Lattice Semiconductor Corporation, the inventor of in-system programmable^TM (ISP^TM) logic products, designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC) and high-performance ISP Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD), Programmable Analog Chips (PAC), and Programmable Digital Interconnect (GDX). Lattice also offers industry leading SERDES products. Lattice provides total solutions for today's system designs by delivering innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

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