Platforms Set for 0.11-Micron Technology Cut Development Time, Cost and Risk
Sunnyvale, California, March 30, 2004 - Fujitsu Microelectronics America, Inc. (FMA) today expanded its AccelArray design architecture, introducing its Embedded CPU platform and five Giga Frame platforms that reduce the cost, time and risks to bring new communications, imaging, networking and storage designs to customers.
The first version of Fujitsu's new Embedded CPU Platform is built around an ARM926 embedded processor architecture widely applied in applications such as metro area and enterprise network systems, medical scanners, ultrasound systems, servers and tape drives. The platform delivers a processor clock speed of 200MHz, with 4Mbits of memory and a gate count that can reach three million. It comes with 16KB I/D cache sub-system and flexible soft bus and peripheral cores.
Along with the ARM926 processor core, Fujitsu will support a suite of soft macros for the Embedded CPU Platform. These macros will include, but are not limited to 10/100/1G and 10G MACs, PCIX, USB controllers and peripheral macros, and a suite of other link-layer macros to address the storage, high-end consumer and networking markets.
Fujitsu's new AccelArray Giga Frames incorporate pre-diffused high-speed Giga PHY (GPHY) macros that provide a point-to-point, full-duplex, differential, serial communications link capable of transferring data at rates ranging from 622Mbps to 3.125Gbps. The GPHY macro is optimal for use as a physical layer to support high-speed protocols in applications that require high bandwidth broadband. Giga Frame platforms offer up to 150Gbps-aggregated bandwidth in full duplex for applications such as high-capacity Ethernet switches, ATM/frame relay switches, routers, aggregation switches, cross-connects and SAN switches.
AccelArray Embedded CPU and Giga Frame Platforms are able to access FMA's rapidly growing library of proven IP cores.
"AccelArray leverages Fujitsu's decades of ASIC design and system-level expertise in the networking and storage market sectors," said Marwan Majid, Director of ASIC marketing for Fujitsu Microelectronics. "We have seen rapid increases in new designs using AccelArray since the beginning of this year, and these new introductions will continue that trend." Over the past year, the AccelArray platform has been used to build devices for telecommunications systems, tape drives, Video-on-Demand (VOD) and ultra-wideband radars.
AccelArray Reduces Cost, Time-to-Market, Design Complexity
The AccelArray architecture eliminates time-consuming design tasks including memory insertion, interface and internal timing closure, signal integrity and Xtalk analysis, and clock tree insertion, among others. AccelArray supports 333MHz core system frequency, with 800MHz analog PLL capability. AccelArray gate counts range from 512,000 to 3.8 million. Using AccelArray, back-end physical design can be completed in four to eight weeks and manufacturing prototypes can take as little as four weeks.
AccelArray also takes advantage of Fujitsu's DDR memory interface technology, which can save significant front- and back-end development time. The programmable DDR macro is tested and in full production in 0.11-micron technology. Fujitsu's design compiler enables address, data path and interface buffer selection for DDR, RLDRAM and QDR-II. The compiler will support DDR-II later in 2004. This feature of AccelArray enables a physical layer interface to design logic and to the data and address buses of the macro DDR1. More than half of AccelArray I/Os can support DDR interface with a Giga platform.
About Fujitsu Microelectronics America
Fujitsu Microelectronics America, Inc. (FMA) leads the industry in innovation. FMA provides high-quality, reliable semiconductor products and services for the networking, communications, automotive, security and other markets throughout North and South America. For product information, visit the company web site at http://www.fma.fujitsu.com/accel/
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