SoC brings satellite-like features to cable

Flying the banner of their new X-Stream product line, the designers at set-top silicon and software vendor Digeo (Kirkland, Wash.) are riding to cable's rescue.

The heart of the X-Stream product is a new 15-million gate system-level IC that combines the functions of about two dozen off-the-shelf components and one ASIC into a single 130-nm chip built by Taiwan Semiconductor Manufacturing Co. Ltd.

The device, which incorporates high-performance A/D converters, extensive signal processing, H.264 compression and decompression, DOCSIS processing and general-purpose embedded CPU cores, forms the hub of a multituner, multidisplay, recording HDTV system.

On the input side, the T2/4 SoC accepts input from up to four tuner modules for video, plus separate input and return channels for DOCSIS and OOB. The chip provides digitization, baseband processing and signal routing for incoming signals. Video is converted to a string of MPEG-2 i-frames on the fly, which are then routed out to a companion chip, and thence to both the display and — through the main system CPU — to the box's hard disk.

This eliminates most of the artifacts of MPEG-2 compression, which are usually related to motion estimation, from the displayed image. As a background task, the system CPU can then pick the stream of i-frames off the disk and route it back through the T2/4 chip for transcoding into the much denser JVT format for longer-term storage on disk.

The chip is designed to work on a motherboard that might be familiar to high-end media PC designers. The reference design includes a 1 GHz Via C3 CPU and accompanying Northbridge. This gives Digeo the processing power to build PC-level graphics and user interfaces in software, using the CPU and Via graphics engine.

The T2/4 chip design includes a bank of MPEG i-frame encoders, dedicated MPEG encode and decode engines and dedicated CPU cores for security, transcoding, transport and conditional access management and real-time control. The CPU cores are IP licensed from ARC Ltd., each instance having its own instruction set extensions for its particular task.

Overall, the chip includes IP from about 15 different vendors. The design was completed in close cooperation with Cadence Design Services, whose engineers were instrumental in generating physical designs for an initial test chip. This provided a learning experience on the 130-nm process and the Cadence tool flow for the Digeo designers, as well as a foundation for the physical design. The design was then gradually brought in-house before tape-out of the final chip.