What's needed for mixed-signal verification (by Bijan Kiani, Synopsys VP of Marketing)

With the increased amount of mixed-signal components in system-on-chip (SoC) designs, verifying functionality, timing and power become critical for first time silicon success. Unless comprehensive and accurate verification is done, companies can spend millions of dollars on silicon re-spins, lose valuable time-to-market, and waste precious design and verification resources. In order to avoid these pitfalls and achieve first silicon success, designers must have a mixed-signal verification solution that meets four key criteria.

First of all, it must have the throughput (performance and capacity) to simulate today's increasingly large designs in a reasonable amount of time, while maintaining an acceptable level of accuracy. Engineers need to simulate multiple process corners to give them confidence in their designs.

During the early phases of the design, engineers need Spice level accuracy to ensure the integrity of critical circuits. Once they reach the full-chip verification phase, a fast Spice simulator will give them the performance and capacity they need to ensure the functionality, timing and power accuracy.

Secondly, today's nanometer IC designs are fabricated using advanced processing technology. To accurately simulate circuit behavior requires highly sophisticated device models that are meticulously characterized using a golden Spice simulator and certified by semiconductor foundries. The same applies to fast Spice simulator.

In order to get accurate full chip simulation, it not only requires the use of models that are foundry certified, but it must also be able to interpret the models the same way as the golden Spice simulator used earlier in the design process. Using the same models from the foundry and interpreting them the same way ensures the highest level of correlation between the Spice and fast Spice simulator results. Third, the verification solution must be tightly linked to a parasitic extraction tool to ensure efficient and accurate post-layout simulation. As process geometries become smaller, parasitic effects become more dominant in circuit behavior making accurate post layout simulation a necessity.

Detailed parasitic extraction often results in large amount of extracted parasitic data, sometimes as much as 10x more than the original design. Traditional "brute-force" approaches that extract parasitic components for the entire chip, and then back-annotate them to the pre-layout design for simulation, are difficult to scale with today's ever-increasing circuit size.

A new integrated verification solution is needed to intelligently provide high capacity and performance for the multi-million gate designs while ensuring highly accurate post layout simulation of the critical circuit components. Only such a tightly integrated solution can deliver the scalability and efficiency for the most demanding post layout simulation.

Finally, the ideal mixed-signal verification environment must be able to concurrently simulate multiple levels of circuit abstractions such as register-transfer, gate, analog behavioral and transistors, and support standard modeling languages such as Verilog-AMS. The solution must have the flexibility of adapting to various design methodologies, whether it is a top-down, bottom-up or a mixed approach. Furthermore, in order to verify complex SoCs — often containing mixed-signal IP blocks — this solution must be able to handle nested multiple analog and digital blocks at any level of design hierarchy.

A verification solution for today's large, mixed-signal SoCs must be able to give engineers the tools they need to satisfactorily simulate their IC designs and still meet the tight time-to-money schedules. Choosing the right mixed-signal verification environment is instrumental in achieving first silicon success.

Bijan Kiani is vice-president of marketing at Synopsys' new ventures business unit.