Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market
IP expectations (by Melissa Jones, President, Ultimodule)
EE Times: Latest News IP EXPECTATIONS | |
Melissa Jones (05/28/2004 4:00 PM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=21400152 | |
The emerging expectation from embedded designers today is that intellectual property will be available not as easy-to-integrate blocks, but in preintegrated combinations. Whether the IP comes as a microcontroller, a system-on-chip with soft processor, a popular set of functions in an ASSP-like device, a reference design for an FPGA implementation, a system-on-module or a single-board, the value is inherent in the time saved.
The phrase designers do not want to hear is nonrecurring engineering charges. They don't have time to integrate IP blocks, but they also don't want to pay extra for final development that brings the solution closest to their ideal requirement. They are willing to settle for something less than the ideal — but not much. They want a solution to use immediately at the lowest possible cost with the closest match to required functionality.
A challenge for both suppliers and designers is to connect and communicate about the right preintegrated combinations for a set of applications or a market segment. Five years ago the vision was that designers would select specific IP elements and piece them together exactly as they wanted — but that hasn't turned out to be the reality. Instead, designers want optimized, virtually standard solutions, whether at the chip level, the system-on-module level or the single-board level. Giving designers greater and greater personal freedom to make specific choices regarding I/O; communications; and bus, memory and even processor performance has turned out to be less the issue than having the right preoptimized solutions available, literally off the shelf, at attractive prices.
The same forces that are driving the preintegration of IP will continue to push at all levels of integration, but it may be fair to say that the emphasis is starting to move away from chips toward systems-on-modules and single-boards. The degree of "mixability" required in today's embedded systems is reaching the point where a solution cannot be supported in a flexible enough way by a single microcontroller or SoC, no matter what its size or sophistication. The good news is that the physical limitations of single-silicon devices can be overcome by systems-on-modules, where the small, adaptable form factor allows a multichip solution that can stand alone or be blended as a daughter card to a single-board solution.
But systems-on-modules or single boards will only be as good as their inherent design flexibility to adapt to chips. The emerging challenge for all manufacturers will be to consider their forward development in ways that allow even faster integration of chips with modules, and, in turn, with single boards. Working to create separate standalone solutions will not be tolerated by the market. Melissa Jones, President, Ultimodule Inc. Sunnyvale, Calif.
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