Pixelworks rolls line of video decoder SoCs
EE Times: Latest News Pixelworks rolls line of video decoder SoCs | |
Mike Clendenin (06/02/2004 9:00 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=21400848 | |
TAIPEI, Taiwan — Pixelworks Inc. is bulking up its line of system-on-chip devices for the advanced display market with the roll out of a family of video decoders this week that will help Asia-based system makers whittle down the number of board designs needed to satisfy divergent standards in Europe and North America. Better known for scaler and deinterlacer technologies, Pixelworks is pushing hard to build a reputation as a provider of video decoder technology, especially among non-Japanese designers of flat-panel TVs in Asia who are eager to use off-the-shelf silicon. To that end, the company is using its new top-of-the-line chip (PW3300) to introduce its DNX 3-D comb filter technology, which works with video signals from both NTSC, the U.S. TV standard and the European PAL standard. "It's important to note that this one chip serves every region because right now that isn't the case," said Chris Bright, a marketing manager at Pixelworks. "If you want to build a TV for Europe [PAL], you need to source a different set of chips versus your NTSC [U.S.]. So this [3-D comb filter] gives you the ability to create one board and one architecture and then through software you can create a TV that serves every region or market that you would want it to." That approach should attract the attention of Asia's original design manufacturers interested in the global TV market, such as Taiwan's BenQ, Tatung, Quanta and Sampo. All are designing televisions for multiple markets, which can mean juggling a dozen or so designs because of the different standards and panel sizes. The higher integration of the SoC could hold even greater appeal for the mid-tier consumer electronics firms in China. Companies like Xoceco, TCL, Haier and Konka are all fiercely competing in China's price-sensitive market, so any amount of integration makes the systems easier to design and cheaper to produce — music to the ears of any engineer, but especially those in the hectic Chinese marketplace. The PW3300 pulls in several discrete chips, including a video decoder, high performance analog/digital converter that ranges up to 150 MHz for processing of a 1,080-line progressive signal input. It also integrates a TMDS receiver and multiplexing functionality. Pixelworks uses software to implement the adaptive sync slicer for extracting Europe's teletext functionality, V-chip protection, close captioning and wide-screen signaling, Bright said. The company is also drawing attention to its SteadySync technology, which helps isolate weak broadcast and cable signals that can be the bane of emerging markets. Pixelworks is also releasing two other chips. The PW2300 targets low- and mid-range LCD TVs and lacks the digital interface of the PW3300. The PW2250 is aimed at TVs and digital projectors, and includes a simpler 2-D comb filter. All three chips use a 256 BGA package. Engineering samples are available and mass production begins in the third quarter.
| |
All material on this site Copyright © 2005 CMP Media LLC. All rights reserved. Privacy Statement | Your California Privacy Rights | Terms of Service | |
Related News
- Pixelworks Licenses ArterisIP FlexNoC Interconnect IP Again for Advanced Video Processing SoCs
- WISchip Rolls Out High-Definition Audio/Video System-On-Chip Decoder for Next-Generation Consumer Electronics
- DisplayPort Rx PHY and Controller IP Cores in multiple Leading Technology Nodes for Next-Generation Video SoCs
- Efinix Rolls Out Line of FPGAs to Accelerate and Adapt Automotive Designs and Applications
- VeriSilicon delivered multi-format hardware video decoder Hantro VC9000D supporting 8K@120FPS VVC/H.266 to customers
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIeâ„¢ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |