SH7 will mix cores and add third cache

SH7 will mix cores and add third cache
By Nick Flaherty, EE Times UK
January 18, 2002 (9:35 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020118S0007

SuperH, the joint venture between Hitachi and STMicroelectronics (ST), is planning to move away from single-processor architecture to a processor with multiple cores.

The SH7 core, being planned for 2005 and built in 0.08µm technology, will have a mix of the previous SH5 and SH6 processor cores, with their own caches. These will be linked to a third system cache by an interconnect derived from the company's current SuperHyway bus.

The move to a multiprocessor is driven by the expectation that multi-threaded operating systems (OSs) such as Windows that will have moved to the embedded market by that time, says Jean Marie Rolland, chief operating officer of SuperH. The company was set up to develop the SH processor architecture independently of the two parents.

"The investment in software is tremendous and our customers are putting a lot of value in software development," he said. "Windows CE.NET might become a multi-thre aded OS in the future, so 2005 is going to be the right time to have this kind of hardware."

SuperH is also developing its own version of the Linux OS to function on such systems.

"We are planning to build SH7 [processors] based on instances of SH6 or SH5 cores and using the multi-threaded layer of the OS to reuse the existing code," he said.

Although this is similar to the approach being taken by com-panies such as Siroyan, the SH5 core already runs off-the-shelf embedded OSs such as Windows CE and Linux.

But there are issues with the system approach. Rolland sees the individual cores controlled directly by the applications to give maximum flexibility to the system chip developers and avoid having to do a different version of the operating system for each chip design.

"Everybody wants the compatibility of existing applications to get to market quickly. But moving from SH5 to 6 or 7 means people will want to use the full capability so they will recompile or repartiti on or even rewrite the code by hand to get to volume production."

He denies that there is a challenge in making a multiprocessor system work: "Our customers, such as ST, are doing it already with an ST20 and an ST40 on the same bus in their set-top boxes."

SuperH is making its chip analysis software available more freely as development tools. This is alongside the compiler and software tool chain development, which is vital for any new architecture.

The SH5, a single instruction issue SIMD [single instruction, multiple data] engine supporting a 32bit instruction set and 64bit data, will be launched in March. The architecture for the SH6, a dual issue version of the SH5, will be announced at the Microprocessor Forum in October.

Both are set to run up to 1GHz and run the existing 16bit SH4 code in a compact mode.