MoSys, TSMC to develop double-density and low-power 1T-SRAMs for embedded use

MoSys, TSMC to develop double-density and low-power 1T-SRAMs for embedded use
By Semiconductor Business News
April 9, 2001 (8:27 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010409S0007

SUNNYVALE, Calif. -- MoSys Inc. here today (April 9) announced a series of new licensing pacts for its 1T-SRAM technology, including a joint-development agreement with Taiwan Semiconductor Manufacturing Co. Ltd. to create new low-power and double-density derivatives of one-transistor memory cells for TSMC's 0.13-micron foundry processes.

Ten-year-old MoSys also announced Applied Micro Circuits Corp. (AMCC) of San Diego has become the latest chip supplier to license the 1T-SRAM technology. The Sunnyvale company said it has extended licensing agreements with Broadcom Corp. and the Galileo Technology division of Marvell Technology Group Ltd. In total, MoSys has now publicly announced 13 licensing pacts for the 1T-SRAM technology, and officials said more than 20 have been inked.

Under the joint-development agreement, TSMC and MoSys plan to create a new low-power version of the embedded memory cell--called 1T-SRAM-M--which will be aimed at syst em-on-chip designs for portable and battery-power applications. A new 1T-SRAM-X derivative will also be developed to double the density of MoSys' current 1T-SRAM cell in embedded memory applications.

"You will be looking at a factor of four-to-six times [the memory density on a chip] over traditional six-transistor SRAM," said Mark-Eric Jones, vice president and general manager of intellectual property (IP) at MoSys.

The 1T-SRAM-M "mobile" memory cell will be available in TSMC's 0.13-micron process technology in the third quarter of 2001. The double-density 1T-SRAM-X technology will be made available to designers in the fourth quarter, said the two companies.

With the new round of agreements, MoSys believes its one-transistor static memory technology is beginning to build momentum in the "manufacturing space" as chip suppliers attempt to address economic issues--especially in the current market conditions, said Jones.

Addressing the amount of silicon taken up by memory is becoming a pressing issue for SoC designs moving into volume production, he said. "Memory is the largest occupier on SoCs. The latest percentages I've seen from Dataquest are in the 30-to-50% range [of the die] and growing," JOne said. "So memory, more than anything else, is determining the cost and economics of these chips."

Jones also said other factors are beginning to play a role in the selection of embedded memory for complex ICs. One that is surprising more chip designers is soft errors, which are caused by alpha particles striking the memory and changing the state of bits in SRAMs, he said.

"A lot of engineers still remember that DRAMs suffered soft errors. They know the problem has been solved and its getting better, but unfortunately, SRAMs are having a much bigger problem with these errors and a lot of designers do not even realize it," he said.

Because the 1T-SRAM is similar in structure to DRAMs, it is far more unlikely to suffer soft errors from alpha particles when feature sizes are shrunk in next-gen eration process technologies than traditional SRAMs, Jones said. This eliminates the need for error correction circuits on chips with embedded SRAM, and that reduces the die size and costs, he said.

AMCC said it plans to apply the 1T-SRAM technology to its next-generation networking ICs for high-speed and optical communications applications. Broadcom in Irvine, Calif., said it will use the 1T-SRAM technology on its Robo switch Ethernet ICs to incorporate higher levels of memory on chip. Galileo Technology in Sunnyvale said it plans to extend its use of the 1T-SRAM to advanced CMOS processes.