VSI Alliance updates virtual component interface spec

VSI Alliance updates virtual component interface spec
By Michael Santarini, EE Times
April 9, 2001 (4:05 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010409S0034

SAN MATEO, Calif. — The Virtual Socket Interface Alliance's On-Chip Bus Development Working Group will release the new version of its Virtual Component Interface Standard this week.

VCI version 2.0 features a new transaction language to facilitate verification and system prototyping, support for a broader range of high-bandwidth cores and several clarifications that make it much easier to understand than version 1.0, said Anssi Haverinen, working-group chairman and research manager at Nokia Research Center (Boston).

Alliance members can access and download the spec from the VSI Alliance Web site.

The on-chip bus group's charter in creating the VCI standard is to provide the design industry with an open, impartial and common on-chip bus interface.

"VCI version 1.0 was for simple peripheral buses and not-so-advanced system buses," said Haverinen. "Version 2.0 is broader and more detailed than the pr evious version."

Haverinen said version 2.0, for example, details the use of out-of-order transactions, which can be used with more-advanced interconnect networks that may require out-of-order transaction execution. "There is also support for advanced arbitration," said Haverinen. "So now interfaces can be more easily connected with a system arbiter. The older version had some support for this, but it required extra work."

New transaction language

Haverinen said the highlight of the 134-page document is a new transaction language that provides virtual-component developers and system-on-chip integrators with a way to use the same test suite for standalone and integrated virtual components without time-consuming test translation and redevelopment of test suites.

"We created the transaction language to make verification of the VCI easier," said Haverinen. "It abstracts the transactions over the VCI and can be used for the simulation and verification of the interface and for documenta tion purposes."

For example, Haverinen said, virtual component providers can create simulation vector sets for their cores that can be tested through the VCI. The integrator can then take those same vectors and integrate them into the system-level testbench and run those same test vectors through the bus while their core is connected to the bus.

Haverinen said another improvement over version 1.0 is support for interconnecting multiple high-bandwidth initiators, such as processors, DSPs, direct memory access controller engines and other real-time, special-application virtual components.

With the release of version 2.0, the working group believes it has "more or less completed its job," Haverinen said. "We had many vendors and users help us create and edit this standard and now we just have to encourage industry adoption."

Haverinen said that once the spec is adopted and any remaining rough spots are addressed, the VCI should be submitted to a formal body like the IEEE.