LSI Logic Demonstrates 12 Gbit/S Serial Interface Circuitry in 90 Nanometer Process Technology
- Increases bandwidth by 400 percent over commonly used SerDes interfaces
- Easy integration into high speed SerDes cores in LSI Logic cell-based ASIC or RapidChip Platform ASIC designs
MILPITAS, Calif., June 14, 2004 -- LSI Logic Corporation (NYSE: LSI) today announced it has tested and validated 12 Gbit/s high-speed serial interface circuits in its G90TM 90-nanometer process technology. LSI Logics G90-based 12 Gbit/s interface technology enables serializer/deserializer (SerDes) cores with quadruple the bandwidth of existing backplanes and double the speed of planned 6 Gbit/s backplane upgrades. This industry-leading solution is designed to meet the requirements of the emerging Optical Internetworking Forum (OIF) CEI 11 LR (Long Reach) standard and provides a leap in performance for storage systems, networking, and telecommunications applications.
With our demonstrated 12 Gbit/s serial interface technology, LSI Logic provides an easy path to increase system bandwidth so that our leading ASIC and RapidChipTM Platform ASIC customers can differentiate their high-speed datacom, telecom, and storage systems designs, said Jean Bou-Farhat, vice president, CoreWare, LSI Logic. We continue to push the leading edge of technology in order to meet customers requirements for time-to-market, performance, reliability and flexibility.
In developing 12 Gbit/s serial interface technology, LSI Logic leveraged its extensive experience in high speed SerDes cores which support a range of applications from 155 Mbit/s SONET traffic to 6.4 Gbit/s backplane links. To achieve these breakthroughs with high-speed SerDes technology in 90 nanometer nodes, the companys high speed mixed signal engineers and packaging engineers worked closely together to provide a system solution with robust signal integrity, a necessary requirement for today's high-speed interfaces.
About CoreWare
The LSI Logic CoreWareTMIP library provides the industrys most comprehensive set of IP solutions that are of proven quality and are designed to work seamlessly with the standard-cell ASIC and RapidChipTM Platform ASIC design flows. Customers can leverage CoreWare IP solutions to significantly reduce risk and turn-around times with complex SoC designs. A dedicated worldwide IP support organization is available to assist customers in all aspects of CoreWare SoC design.
About LSI Logic Corporation
LSI Logic Corporation (NYSE: LSI) is a leading designer and manufacturer of communications, consumer and storage semiconductors for applications that access, interconnect and store data, voice and video. In addition, the company supplies storage network solutions for the enterprise. LSI Logic is headquartered at 1621 Barber Lane, Milpitas, CA 95035. http://www.lsilogic.com.
|
Related News
- ARM Announces First Production-Ready DDR1 And DDR2 Memory Interface IP On TSMC 90-Nanometer Process
- LSI Logic Shatters Previous Density/Performance Boundaries With 90 Nanometer RapidChip Platform ASICs
- LSI Logic Simplifies High-Speed Serial Interface Design with Expanded Rapidchip Xtreme Family of Platform ASICs
- MoSys Ports 1T-SRAM-Q Technology to NEC Electronics' 90-Nanometer Logic Process; Initial Silicon Verification Achieved for 1T-SRAM-R, in Fabrication for 1T-SRAM-Q
- Agere Systems Demonstrates Fastest SerDes Circuitry Utilizing 90 Nanometer Low-K Technology
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |