Virage Logic Introduces Ultra-Low-Power Semiconductor IP Platform, Allowing Up to 20X Reduction in Static, 80 Percent in Dynamic Power Dissipation

FREMONT, Calif., June 28, 2004 — One of the unrelenting challenges facing system-on-chip (SoC) designers today is power management, particularly in low-power, battery-operated microelectronics that serve as the basis for any number of ubiquitous consumer electronics products such as cell phones, personal digital assistants (PDAs) and handheld gaming platforms.  Ironically, the one element in SoCs that has not shrunk along with process geometries is static power.  In fact, it has grown exponentially, in inverse proportion to the overall size of the SoC.  To help designers address this challenge, Virage Logic Corp. (Nasdaq:  VIRL), a leading provider of best-in-class semiconductor IP platforms, today announced IPrima Mobile, an application-optimized semiconductor IP platform that significantly minimizes and effectively manages power dissipation without paying a performance penalty.  IPrima Mobile is the first offering in Virage Logic’s IPrima family of application-optimized semiconductor IP platforms.

“Portable consumer and wireless personal communication products will be market drivers for the semiconductor industry over the next five years.  Growth rates for many of these products will average more than 30 percent annually,” said Morry Marshall, vice president strategic technologies at Semico Research Corporation.  “The potential power savings and longer battery life offered by the IPrima Mobile platform will provide a real competitive advantage to Virage Logic’s customers.” 

The IPrima family of application-optimized semiconductor IP platforms brings together a wide range of technology-leading IP components in a single, integrated IP platform comprising memories, logic and I/Os.  IPrima Mobile enables a broad range of power management methods to control both static and dynamic power consumption; including such advanced optimization techniques as full block-level voltage islands, clock gating, mixed-transistor threshold voltage support, voltage frequency scaling, back biasing and state retention standby mode.  With IPrima Mobile, designers can determine the optimum level of power dissipation reduction for their application’s performance requirements.

“IPrima Mobile builds on Virage Logic’s three-plus years of silicon-proven low-power IP products to provide SoC designers with a single, integrated IP platform that enables them to efficiently develop consumer products with longer battery life and lower electromagnetic interference (EMI) emissions,” said Jim Ensell, vice president of marketing at Virage Logic.  “By delivering up to 20X reduction in static and 80 percent reduction in dynamic power dissipation, IPrima Mobile gives our customers the ability to rocket past their competitors in terms of battery life, one of the key features consumers care about.”

“We have used Virage Logic memories with many of our designs; however, our latest SignaKlara™ embedded technology used in a wide range of portable and wearable devices required ultra-low-power and ultra-miniature IP,” said Peter Balsiger, president of Dspfactory SA.  “We selected the IPrima Mobile memories and standard cells after an extensive evaluation resulted in significant power and area savings that are required for our latest designs.”

To fully maximize IPrima Mobile’s advanced power-optimization features, Virage Logic has established strategic partnerships with leading electronic design automation (EDA) tools developers, IP companies and foundries.  This ensures a complete and reliable design flow, support for protocols such as the ARM® Intelligent Energy Management™ (IEM) technology, and optimization of performance and energy dissipation with respect to manufacturing costs. 

“Optimizing power consumption has become a system-level issue.   To generate the best combination of optimal energy dissipation and adequate computing performance, enhanced EDA tools and optimized IP platforms must work smoothly together,” said Eric Filseth, vice president of marketing for digital IC implementation at Cadence Design Systems.  “Virage Logic’s IPrima Mobile was designed to work with our Cadence Encounter low-power design flow, the leading solution to analyze and optimize power for nanometer designs.”

About Virage Logic’s IPrima Mobile Platform
The Virage Logic IPrima Mobile platform includes:

• Area, Speed and Power (ASAP) Memory™ Ultra-Low-Power (ULP) Memories   - single- and dual-port ASAP SRAMs; single- and dual-port STAR (Self-Test and Repair) SRAMs; single- and dual-port RF (Register Files) and Read Only Memories (ROM).

• ASAP Logic™ Ultra-Low-Power (ULP) Standard Cell Library   - Based on the ASAP Logic patented routing methodology and cell architecture and the Ultra-High-Density (UHD) Standard Cell set, the ULP Library typically provides up to 30 percent improvement in area when compared to conventional standard cell libraries while consuming 20 percent less dynamic and 7X less static power at nominal voltage thresholds.  Level shifters are included as part of the ULP Library for power management.

• Base I/O Cells and Mixed-Signal Blocks - Extended operating voltage range CMOS buffers; SSTL-2 Class I and II; HSTL Class I and II; PCI and PCI-X transceivers; and USB1.1 

About Virage Logic’s IPrima Family of Application-Optimized Platforms
Virage Logic’s IPrima family of application-optimized semiconductor IP platforms delivers integrated, technologically advanced and differentiated IP and supports well-defined system-level design methodologies targeted to specific market applications.  The IPrima Platforms meet the critical requirements of reducing SoC costs, boosting performance and ensuring reliability, while satisfying shrinking development budgets and improving time-to-profitability.  Virage Logic’s IPrima family of application-optimized platforms include products for market segments such as consumer, data communications and networking, computer and graphics, and portable and handheld. The IPrima platforms include optimized components such as:

• Memory IP products crafted for application-specific requirements in terms of type, size, area, performance and power dissipation

• Standard Cell libraries to implement customer-specific differentiation and high-value system blocks

• Input/Output (I/O) cells for basic and high-performance, application-specific interfaces

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SAFEHARBORSTATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE SECURITIES LITIGATION REFORM ACT OF 1995:

Safe Harbor Statement under the Private Securities Litigation Reform Act of 1995:
Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to trends, business outlook, products, and customer relationships.  Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements.  These risks and uncertainties include Virage Logic’s ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic’s ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic’s ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic’s technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company’s ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company’s ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company’s Annual Report on Form 10-K for the period ended September 30, 2003, and in Virage Logic’s other periodic reports filed with the SEC, all of which are available from Virage Logic’s website (www.viragelogic.com) or from the SEC’s website (www.sec.gov), and in news releases and other communications.  Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release. 

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