Carbon, CoWare link RTL to SystemC

The link allows users to validate RTL versions of their designs in CoWare's SystemC simulation environment. It thus makes it possible to swap between architectural and RTL models, and to bring legacy IP into a SystemC simulation, according to representatives of both companies.

Users feed Carbon's SpeedCompiler software synthesizable Verilog code, and the tool generates a high-performance engine — called DesignPlayer — that now includes an optional SystemC wrapper.

Carbon claims DesignPlayer models are cycle and register accurate, and comparable in speed to designs running on hardware emulation. Thus, transferring designs into DesignPlayer models and running them with ConvergenSC will allow hardware engineers to quickly validate their RTL designs meet system specifications, and allow software engineers to get an early jump on validating software drivers, diagnostics and firmware, according to Carbon.

Carbon