Power management movement shows energy

Fremont, Calif. - In response to pressing demands from chip designers, a framework for managing the power consumption of designs at 130 nanometers and below is beginning to emerge. Like the underlying problem, the framework has two branches: dynamic power control and leakage power control. The need for innovations and their implications extend across a spectrum that includes process, library and software development camps.

This is frustrating for hardware personnel: while there are important steps that process engineers, library developers and IC design teams can take to help control energy use in end systems, none of those measures makes much difference without the cooperation of OS and application developers. Nothing thus far suggests that such cooperation is likely to occur.

Nonetheless, all parties on the hardware side are soldiering on. A case in point is Virage Logic Corp.'s introduction of the IPrima Mobile low-power libraries aimed specifically at designs in which energy consumption is important enough to justify some sacrifice in performance and perhaps die area.

With this priority in mind, Virage Logic (Fremont, Calif.) pulled out all the stops, creating a set of memory, logic and I/O libraries that are inherently low in dynamic power and that support all of the currently popular techniques for further reducing both dynamic and leakage-related energy consumption.

The range of accepted techniques is now fairly extensive. It includes transistors with different threshold voltages, voltage scaling, frequency scaling, substrate biasing (also known as back-biasing) and creation of voltage islands. In addition, other techniques are used on memory structures.

The most widely used approach, and simplest for library designers to adopt, involves multiple threshold voltages. Most new processes, including Taiwan Semiconductor Manufacturing Co. Ltd.'s 130-nm process supported by the IPrima libraries, offer a choice of transistors with low or with higher threshold voltages. Low-threshold devices are faster and leakier. By designing two sets of cells with identical footprints, library developers allow chip designers to create an entire design with low-leakage cells, and then go back through the design and drop in high-speed cells on nets with negative timing slack. That can significantly affect static power consumption.

These techniques have major implications for libraries. The cells have to be characterized at a number of operating voltage points. That means structures identified in the design rules as only applicable for full-voltage operation-say, transistor stacks-have to be eliminated. And it means a lot of additional corners to check in simulation and silicon validation.

Ideally, the cells would be characterized across a continuous range of voltages, but neither silicon characterization techniques nor library formats are ready for this, according to Virage senior director of product marketing Brani Buric. So for now users will have to get by with an increased number of corners rather than a continuous timing, power and temperature model.

In addition, provision has to be made for the block to be electrically isolated from its neighbors and correspondents. That means separate power supply lines and quite possibly ground lines, and it means level-shifting cells for signals that enter or leave the block. This in turn has an interesting implication for Virage's seven-grid cells, which are reduced in height as part of a speed-for-power trade. The level-shifter cells are designed to be double-height so they can easily contact two different power rails, thus avoiding huge disruptions to the power grid to deal with routing of two or more different voltages.

As a final-and difficult-step, some teams have begun to use substrate biasing to reduce leakage. In this technique, a circuit is made quiescent. Then the substrate under the channels of the transistors is biased to in effect pinch off the subthreshold leakage current that would have flowed through the channel. Virage estimates that this can reduce leakage by a factor of seven in blocks where it is used uniformly.

But this is not a trivial technique. If used on a block-by-block basis, it means that the substrate under the block has to be isolated from the bulk silicon, and that contacts from at least some cells have to be driven through to the substrate-which means that room has to be found in the cells for those contacts without violating spacing rules or disrupting routing. It means that yet another voltage-a substrate bias-has to be provided and routed through the cell rows.

How much difference do all these techniques and others make? The answer depends on how thoroughly chip designers use each technique, on the architecture of the chip, and, critically, on how fully software developers are brought into the process. Virage estimates that in deeply embedded designs, where a great deal is known about the performance profile of the application, dynamic power savings can be as great as 80 percent, and static power can be reduced by as much as a factor of 20. In applications with changing software loads, such as PDAs, those numbers may drop to as much as 30 percent and a factor of seven, respectively.

The IPrima platform of libraries is available now. Platform license fees begin at $150,000.