Philips points Target compilation at Coolflux DSP

![]() ![]() | |
EE Times: Latest News Philips points Target compilation at Coolflux DSP | |
Peter Clarke (07/07/2004 11:24 AM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=22104087 | |
TOKYO -- Royal Philips Electronics NV has started distributing a compiler-centric software development kit for the CoolFlux DSP core, according to Target Compiler Technologies NV on Wednesday (July 7). The software development kit, "Checkmate for CoolFlux DSP", was developed by Target Compiler Technologies as a processor-specific instantiation of Chess/Checkers, which is a tool suite for the creation of application-specific processor cores. The CoolFlux DSP is a 24-bit DSP core available for technology licensing from Philips Intellectual Property & Standards (IP&S) and also distributed through the StarIP program in the DesignWare library of Synopsys Inc. Checkmate for CoolFlux DSP contains both programming and verification tools. According to Philips, one of CoolFlux DSP's distinguishing features is that it is designed for best C compiler performance. "We wanted our new DSP to outperform other solutions, not only in terms of power consumption and cost, but by offering very efficient C programmability at the same time", said Johan Van Ginderdeuren, business development manager at Philips Digital Systems Labs (Leuven, Belgium), in a statement. "For audio applications, assembly programming has often been deemed mandatory to meet the ultra-low power requirements. However, the CoolFlux DSP product has shown us the key to compiler friendly low-power design, which is the use of retargetable compilation technology," Van Ginderdeuren added. "Our patented graph-based compilation technology enables full use of instruction level parallelism, pipelining, and the heterogeneous aspects of embedded processor architectures", said Gert Goossens, chier executive officer of Target. "This results in highly optimal compiled code, both from a cycle and code density perspective, comparable to hand-optimized assembly code." "The Checkmate toolkit is already being used by CoolFlux DSP's lead customers and a free evaluation license is available via Philips for one month, and also to subscribers of Synopsys' DesignWare Library," said Tony Picard, Target's vice president of sales and marketing, in the same statement.
| |
All material on this site Copyright © 2005 CMP Media LLC. All rights reserved. Privacy Statement | Your California Privacy Rights | Terms of Service | |

Related News
- Synopsys and Philips Announce New Philips' CoolFlux DSP Core to be Distributed in Synopsys' DesignWare Library
- DSP Group Unveils SparkPA, Highest RF Transmit Power CMOS Power Amplifier (PA) for 802.11ac Access Points Using TSMC Standard CMOS Process
- Malaspina Labs VoiceBoost Integrates into NXP's CoolFlux DSP Core
- Rubidium Voice Trigger and Speech Recognition Integrates into NXP's CoolFlux DSP Core
- Cochlear Adopts Target's Optimizing C Compiler Technology for its Ultra-Low Power Hearing Implant DSP
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |