English
TriCN Offers Most Area Efficient x1 PCI Express PHY
True Single Lane Design Provides Significant Area Savings Over Competition
SAN FRANCISCO, CA - August 2, 2004 - TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology, today announced that it has established an industry precedent with the most area-efficient single lane (x1) PCI Express PHY. Currently available in the TSMC 130nm process, TriCN's PCI Express PHY x1 is the first to achieve a size of only 0.68 sq. mm for the PIPE core, by far the smallest in the industry.
"While today's announcement marks another significant 'industry first' for TriCN, it represents an even bigger win for semiconductor designers who are constantly seeking to reduce area consumption, especially in consumer applications," explains Ron Nikel, co-founder and Chief Technical Officer with TriCN. "This is exactly what our PCI Express PHY is designed to do. Based on our analysis of the market, we believe our single lane PCI Express PHY is nearly 40% smaller than the nearest competitor."
In June 2004, TriCN introduced its PCI Express PHY product family that supports all lane configurations, including x1, x2, x4, x8, x12, x16 and x32. What differentiates TriCN's x1 lane configuration is its true x1 design. This is a departure from many competing offerings that simply disable multi-lane PHYs, penalizing customers with unnecessary area overhead.
TriCN's PCI Express X1 PHY
TriCN PCI Express PHYs are PIPE 1.0a compliant, and include the SerDes, the PIPE logic and the I/Os. The products are delivered as a hard macro requiring no further RTL synthesis, significantly reducing engineering time and risk over comparable solutions with soft IP components. The TriCN PCI Express PHYs support lane reversal, per-lane at-speed internal loop back BIST, and both 250MHz/8 bit per lane and 125 MHz/16 bit per lane native interfaces.
Availability
TriCN's PCI Express x1 PHY is immediately available in the TSMC 130nm process.
About TriCN
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip. All products are designed using rigorous signal integrity and timing analysis to ensure first time power-up success. Products include Base I/O libraries for pad-ring creation, high-performance memory and networking interfaces, multi-function I/O's compatible with multiple interface protocols, and multi-gigabit PHY products. TriCN's customers range from fabless semiconductor to systems companies and IDMs.
All trademarks mentioned herein are the property of their respective owners.
SAN FRANCISCO, CA - August 2, 2004 - TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology, today announced that it has established an industry precedent with the most area-efficient single lane (x1) PCI Express PHY. Currently available in the TSMC 130nm process, TriCN's PCI Express PHY x1 is the first to achieve a size of only 0.68 sq. mm for the PIPE core, by far the smallest in the industry.
"While today's announcement marks another significant 'industry first' for TriCN, it represents an even bigger win for semiconductor designers who are constantly seeking to reduce area consumption, especially in consumer applications," explains Ron Nikel, co-founder and Chief Technical Officer with TriCN. "This is exactly what our PCI Express PHY is designed to do. Based on our analysis of the market, we believe our single lane PCI Express PHY is nearly 40% smaller than the nearest competitor."
In June 2004, TriCN introduced its PCI Express PHY product family that supports all lane configurations, including x1, x2, x4, x8, x12, x16 and x32. What differentiates TriCN's x1 lane configuration is its true x1 design. This is a departure from many competing offerings that simply disable multi-lane PHYs, penalizing customers with unnecessary area overhead.
TriCN's PCI Express X1 PHY
TriCN PCI Express PHYs are PIPE 1.0a compliant, and include the SerDes, the PIPE logic and the I/Os. The products are delivered as a hard macro requiring no further RTL synthesis, significantly reducing engineering time and risk over comparable solutions with soft IP components. The TriCN PCI Express PHYs support lane reversal, per-lane at-speed internal loop back BIST, and both 250MHz/8 bit per lane and 125 MHz/16 bit per lane native interfaces.
Availability
TriCN's PCI Express x1 PHY is immediately available in the TSMC 130nm process.
About TriCN
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip. All products are designed using rigorous signal integrity and timing analysis to ensure first time power-up success. Products include Base I/O libraries for pad-ring creation, high-performance memory and networking interfaces, multi-function I/O's compatible with multiple interface protocols, and multi-gigabit PHY products. TriCN's customers range from fabless semiconductor to systems companies and IDMs.
All trademarks mentioned herein are the property of their respective owners.
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