Amba bus addition promises to boost bandwidth

Amba bus addition promises to boost bandwidth
By Chris Edwards, EE Times UK
March 22, 2001 (6:11 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010322S0053

LONDON — ARM Ltd. says that an addition to its Amba on-chip hardware bus, or AHB, will let designers multiply the total bandwidth available in a system without changing the bus interface on existing intellectual-property cores.

The additional capabilities should help the ARM Modular Bus Architecture get selected more often in a wider variety of applications including networking systems and automotive electronics, the company said.

Use of the standard is free and a copy of the specification can be downloaded from ARM's Web site. This appendix to the AHB 2.0 spec can be used without royalty or other charges but is subject to a license agreement intended to preserve the integrity of the specification. ARM (Cambridge, England) does sell MicroPack, a design environment intended to help build Amba-compliant cores and systems.

To boost overall bandwidth, the company has now made it possible to interpose a swit ch matrix between AHB 2.0 masters and slaves that in effect puts multiple buses between them.

At the same time, the company has developed a cut-down version of the AHB interface that master cores can use if they do not need to support the full range of transactions.

"The way we are packaging this is as an appendix to the Amba [hardware bus] 2.0 specification. AHB is still central to our interconnect strategy," said Jonathan Morris, MicroPack product manager for ARM.

ARM is calling the switch matrix-enhanced version of the bus "multilayer AHB" and the slimmed-down version "AHB-Lite." Typically, the company expects AHB-Lite to be used where support for arbitration between multiple masters is not needed.

Masters, slaves

Both standard and AHB-Lite cores can plug into the switch matrix as bus masters. Standard slaves are also compatible with the matrix. The bus arbiter sits in the matrix and controls the way in which ports are switched to and from masters and slaves.

Designers have control over how often the arbiter switches the matrix to create virtual buses between each master and its target.

"We would expect people to switch on a burst basis, but you can switch on each bus transaction efficiently," said Bruce Mathewson, Amba technical leader at ARM. "It is easier to verify if you switch on each transaction."

Mathewson said multilayer AHB helps avoid the need to work with complex split transactions, where the initial request is a separate bus action from the transfer that returns the required data. He said that designers can choose how many switched buses the central matrix supports. "You don't need to have a full interconnect matrix. You can have a trade-off between complexity and potential bandwidth," he said.

Morris said cores do not have to connect directly to the switch matrix. A master may have several slaves on a local bus with a further set, accessible by other masters, on the other side of the matrix. It is also possible to have multiple masters sharing a port on the matrix.

He said the company is working with customers in the networking world but other application areas have helped drive the multilayer additions to the AHB specifications.

Notably, "Automotive customers helped pull it through," said Morris.

The next version of the MicroPack product, due in April, will support the multilayer AHB as a parameterizable soft core.

Also in MicroPack is a wrapper that gives any core supporting the AHB-Lite specification the extra functions needed to turn it into a full AHB master.

Chris Edwards is the editor of Electronics Times, EE Times' sister publication in the United Kingdom.