TSMC launches royalty-tracking system for IP cores in chips

TSMC launches royalty-tracking system for IP cores in chips
By Semiconductor Business News
March 20, 2001 (6:57 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010320S0080

HSINCHU, Taiwan--In a series of design automation announcements, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) today said it has become the first IC manufacturer to automatically track the use of third-party intellectual property (IP) in chips.

The IP-tagging system tracks royalty for design cores using standards from the Virtual Socket Interface Association (VSIA) and information from TSMC's Total Order Management (TOM) system. The new system generates usage reports for both the foundry chip customer and the IP developer, said TSMC in Hsinchu.

"The VSIA standard provides a simple method for identifying IP blocks within a design," said Silphy Ou, IP program manager at TSMC's North American subsidiary in San Jose. Ou added, "We can do a lot with the small amount of information that is extracted from the chip."

The system can help designers to avoid mistakes by identifying outdated IP revisions before a photomask is created. "Similar ly, we can give IP providers hard data about the manufacturing yields for their IP cores," Ou added.

Also today, TSMC announced a design library evaluation flow intended to minimize guesswork in selecting libraries, and the foundry company launched a new initiative to share data on silicon substrates with design tool suppliers to address cross-talk problems in 0.25- and 0.18-micron mixed-signal ICs.

TSMC said it was sharing critical mixed-signal process data with Cadence Design Systems Inc. and Simplex Solutions Inc. to improve the analysis capability in system-on-chip (SoC) designs. "SoC devices with a mix of analog and digital circuitry are finding their way into wireless systems, networking, multimedia and other popular applications," noted Andrew Moore, design services marketing manager at TSMC.

"By providing our substrate data to these EDA companies, designers will have another means to automate the design of PLLs [phase-locked loops], filters, and other critical mixed-signal and RF blocks, " he said.

The SeismIC tool from Cadence and the SubstrateStorm tool from Simplex create simulation models for the substrate of ICs. TSMC said designers can use these models to quickly try different layout and isolation techniques to minimize contamination of noise-sensitive blocks.

TSMC said its new design library evaluation flow is the industry's "only documented process for selection of third-party libraries." The evaluation flow is intended to give designers early access to libraries and direct access to library vendors for financial agreements and technical services, said the foundry company.

"Every IC design has its own very specific library specifications, so finding the right library for the job can be a complicated process with plenty of surprises along the way," said Kurt Wolf, director of TSMC's Library Alliance program. "The TSMC Library-9000 Evaluation Flow program takes much of the guesswork out of this process, providing the designer with the best available foundry experience."

Together, the designers, library vendors, and TSMC are laying the groundwork for next-generation SoC designs."

TSMC said it has partnered with six library vendors to offer a range of process-specific design libraries. The libraries--from Artisan, Avanti, NurLogic, Virage Logic, Virtual Silicon and Xemics, support roadmaps for multiple process generations including various combinations of 0.25-, 0.18-, and 0.15- and 0.13-micron technologies, said TSMC.