Mentor and Denali Collaborate to Deliver High-Quality IP for PCI Express and Advanced Switching Interfaces
Mentor's PCI Express and Advanced Switching Cores Verified with Denali PureSpec
PALO ALTO, Calif., August 30, 2004 -- Denali Software Inc. and Mentor Graphics Corporation (Nasdaq: MENT - News) today announced a collaborative effort to ensure high quality and ease of deployment for the Mentor Graphics® PCI Express intellectual property (IP) cores. Mentor Graphics will use Denali's PureSpec verification IP product to confirm its PCI Express IP core is compliant with the PCI Express and Advanced Switching Interconnect (ASI) interface standards, and interoperable with other system designs. Through this effort, Mentor will provide its customers with the highest possible quality IP, while lowering the cost of deployment and integration.
"Denali is a leader in verification solutions for PCI Express and Advanced Switching designs and we are pleased to collaborate with them on this effort," said Michael Kaskowitz, general manager, Intellectual Property Division, Mentor Graphics. "Compliance and interoperability are key requirements for success and this collaboration will move us a long way towards this goal. Working with Denali, we are able to increase the quality and efficiency of our PCI Express and ASI capable IP solutions, while strengthening the Denali solution by sharing our knowledge and experience as a leading IP provider."
Adds Denali's Chief Technology Officer Mark Gogolewski: "Mentor Graphics PCI Express IP provides an excellent foundation for Advanced Switching solutions. Our role is to provide our customers with the highest quality verification IP to enable fast efficient development of these critical interfaces. A key part of this enablement is to work with leaders like Mentor to ensure that our mutual customers can seamlessly integrate and verify the Mentor IP in the customers design environment."
About Mentor Graphics PCI Express IP
- Scalable architecture: x1, x2, x4, x8, x12, x16 lanes at 2.5Gbps
- Supports PCI Express endpoint, bridge, switch and root complex applications
- Low latency implementation
- Power management, AER, hot plug, multiple links per port
- Up to 4,096 byte packets for Tx & Rx and retry buffers
- 64 or 128 bit FIFO based back-end interface
- 8 or 16 bit PIPE interface to SerDes PHY
- Full support for ASI in the Data Link Layer, which may be used independently of the Transaction Layer.
About Denali PureSpec Verification IP
PureSpec is the most widely used verification IP product for simulating and verifying PCI Express and Advanced Switching Interconnect designs. PureSpec models all devices in the PCI Express topology, including the root complex, switch, endpoint and PCI Express to PCI bridge. Within PureSpec, all protocol layers -- physical, data link and transaction -- of the PCI Express/ASI specification are modeled and can be simulated concurrently or independently. PureSpec contains thousands of assertions which are monitored during simulation to ensure compliance with the specification and interoperability with other system devices. PureSpec provides seamless integrations to EDA tools and verification language, and is available for customer evaluation at: www.denali.com/purespec
About Denali Software, Inc.
Denali Software Inc. is the world's leading provider of electronic design automation (EDA) tools and semiconductor intellectual property (SIP) solutions for chip interface design and verification. More than 400 companies worldwide use Denali's tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. For more information, please visit Denali at www.denali.com. Or, contact Denali by phone at: (650) 461-7200.
The Denali logo, Databahn, eMemory, MMAV, and PureSpec are trademarks of Denali Software Inc. PCI Express is a trademark of PCI-SIG. All other trademarks are the property of their respective owners.
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